參數(shù)資料
型號: DS2196LN
元件分類: 通信及網絡
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù): 88/157頁
文件大?。?/td> 734K
代理商: DS2196LN
DS2196
88 of 157
15.1 BERT REGISTER DESCRIPTION
BC0: BERT CONTROL REGISTER 0 (Address = 40 Hex)
(MSB)
(LSB)
RESYNC
TINV
RINV
PS2
PS1
PS0
LC
SYMBOL
TINV
POSITION
BC0.7
BC0.6
NAME AND DESCRIPTION
Not Assigned.
Should be set to 0 when written to.
Transmit Invert Data Enable (TINV).
0 = do not invert the outgoing data stream
1 = invert the outgoing data stream
Receive Invert Data Enable (RINV).
0 = do not invert the incoming data stream
1 = invert the incoming data stream
Pattern Select Bit 2.
Refer to Table 15-1 for details.
Pattern Select Bit 1.
Refer to Table 15-1 for details.
Pattern Select Bit 0.
Refer to Table 15-1 for details.
Load Bit and Error Counters (LC).
A low to high transition
latches the current bit and error counts into the host accessible
registers BBC0/BBC1/BBC2/BBC3 and BEC0/BEC1/BEC2
and clears the internal count. This bit should be toggled from
low to high whenever the host wishes to begin a new
acquisition period. Must be cleared and set again for a
subsequent loads.
Force Resynchronization (RESYNC).
A low to high
transition will force the receive BERT synchronizer to
resynchronize to the incoming data stream. This bit should be
toggled from low to high whenever the host wishes to acquire
synchronization on a new pattern. Must be cleared and set
again for a subsequent resynchronization.
RINV
BC0.5
PS2
PS1
PS0
LC
BC0.4
BC0.3
BC0.2
BC0.1
RESYNC
BC0.0
相關PDF資料
PDF描述
DS21Q43AT Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
DS21Q43ATN Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
DS21Q44 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
DS21Q44T Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
DS21Q44TN MICROSWITCH, SPDT, SIM ROLLER LEVER; Current, contact AC:5A; Force, operating:91.75gf; Travel, pre:16.0mm; Centres, fixing LxW:22.2mm; Temp, op. max:120(degree C); Temp, op. min:-40(degree C); Length / Height, external:9.25mm; Width, RoHS Compliant: Yes
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