參數(shù)資料
型號: DS2196LN
元件分類: 通信及網(wǎng)絡
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù): 119/157頁
文件大?。?/td> 734K
代理商: DS2196LN
DS2196
119 of 157
Normally, the clock that is output at the RCLKLO pin is the recovered clock from the T1 AMI/B8ZS
waveform presented at the RTIP and RRING inputs. When no AMI signal is present at RTIP and
RRING, a Receive Carrier Loss (LRCL) condition will occur and the RCLKLO will be sourced from the
clock applied at the MCLK pin. If the jitter attenuator is either placed in the transmit path or is disabled,
the RCLKLO output can exhibit slightly shorter high cycles of the clock. This is due to the highly over
sampled digital clock recovery circuitry. If the jitter attenuator is placed in the receive path (as is the case
in most applications), the jitter attenuator restores the RCLK to being close to 50% duty cycle. Please see
the Receive AC Timing Characteristics in Section 22 for more details.
19.2 TRANSMIT WAVESHAPING AND LINE DRIVING
The DS2196 uses a set of laser–trimmed delay lines along with a precision Digital–to–Analog Converter
(DAC) to create the waveforms that are transmitted onto the T1 line. The waveforms created by the
DS2196 meet the latest ANSI, AT&T, and ITU specifications. See Figure 19–3. The user will select
which waveform is to be generated by properly programming the LBOS3/LBOS2/LBOS1/LBOS0 bits in
the Line Interface Control Register (LICR). The DS2196 can set up in a number of various
configurations depending on the application. See Table 19–1 and Figure 19–1.
Table 19-1:
LINE BUILD OUT SELECT IN LICR
LBO
S3
0
0
0
0
0
0
0
0
1
1
LBO
S2
0
0
0
0
1
1
1
1
0
0
LBO
S1
0
0
1
1
0
0
1
1
0
0
LBO
S0
0
1
0
1
0
1
0
1
0
1
LINE BUILD OUT
APPLICATION
0 to 133 feet/
133 feet to 266
266 feet to 399
399 feet to 533
533 feet to 655
–7.5 dB
–15 dB
–22.5 dB
Square Wave Output
Open Drain Output Driver
Enable
DSX–1/0dB CSU
DSX–1
DSX–1
DSX–1
DSX–1
CSU
CSU
CSU
Custom Wave shape
Custom Wave shape
NOTE:
LBOS3 is located at CCR7A.0.
Due to the nature of the design of the transmitter in the DS2196, very little jitter (less then 0.005 UIpp
broadband from 10 Hz to 100 kHz) is added to the jitter present on TCLKLI. Also, the waveforms that
they create are independent of the duty cycle of TCLKLI. The transmitter in the DS2196 couples to the
T1 transmit twisted pair via a 1:2 step up transformer for the as shown in Figure 19–1. In order for the
devices to create the proper waveforms, this transformer used must meet the specifications listed in Table
19–2.
相關PDF資料
PDF描述
DS21Q43AT Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
DS21Q43ATN Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
DS21Q44 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
DS21Q44T Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
DS21Q44TN MICROSWITCH, SPDT, SIM ROLLER LEVER; Current, contact AC:5A; Force, operating:91.75gf; Travel, pre:16.0mm; Centres, fixing LxW:22.2mm; Temp, op. max:120(degree C); Temp, op. min:-40(degree C); Length / Height, external:9.25mm; Width, RoHS Compliant: Yes
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