參數(shù)資料
型號(hào)： DS2196LN
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 118/157頁
文件大?。?/td> 734K
代理商： DS2196LN
DS2196
118 of 157
19. LINE INTERFACE FUNCTION
The line interface function in the DS2196 contains three sections; (1) the receiver which handles clock
and data recovery, (2) the transmitter which wave shapes and drives the T1 line, and (3) the jitter
attenuator. Each of these three sections is controlled by the Line Inter-face Control Register (LICR)
which is described below.
LICR: LINE INTERFACE CONTROL REGISTER FRAMER A
(Address = 7C Hex)
(MSB)
LBOS2
(LSB)
TPD
LBOS1
LBOS0
EGL
JAS
JABDS
DJA
SYMBOL
LBOS2
POSITION
LICR.7
NAME AND DESCRIPTION
Line Build Out Select Bit 2.
Sets the transmitter build out; see
the Table 19–1
Line Build Out Select Bit 1.
Sets the transmitter build out; see
the Table 19–1
Line Build Out Select Bit 0.
Sets the transmitter build out; see
the Table 19–1
Receive Equalizer Gain Limit.
0 = –36 dB
1 = –15 dB
Jitter Attenuator Select.
0 = place the jitter attenuator on the receive side
1 = place the jitter attenuator on the transmit side
Jitter Attenuator Buffer Depth Select.
0 = 128 bits
1 = 32 bits (use for delay sensitive applications)
Disable Jitter Attenuator.
0 = jitter attenuator enabled
1 = jitter attenuator disabled
Transmit Power Down.
0 = normal transmitter operation
1 = powers down the transmitter and 3-states the TTIP and
TRING pins
LBOS1
LICR.6
LBOS0
LICR.5
EGL
LICR.4
JAS
LICR.3
JABDS
LICR.2
DJA
LICR.1
TPD
LICR.0
19.1 RECEIVE CLOCK AND DATA RECOVERY
The DS2196 contains a digital clock recovery system. See the DS2196 Block Diagram in Section 1 and
Figure 19–1 for more details. The DS2196 couples to the receive T1 twisted pair via a 1:1 transformer.
See Table 19–2 for transformer details. The 1.544 MHz clock attached at the MCLK pin is internally
multiplied by 16 via an internal PLL and fed to the clock recovery system. The clock recovery system
uses the clock from the PLL circuit to form a 16 times over sampler, which is used to recover the clock
and data. This over sampling technique offers outstanding jitter tolerance (see Figure 19–2).
相關(guān)PDF資料
PDF描述
DS21Q43AT Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
DS21Q43ATN Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
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DS21Q44TN MICROSWITCH, SPDT, SIM ROLLER LEVER; Current, contact AC:5A; Force, operating:91.75gf; Travel, pre:16.0mm; Centres, fixing LxW:22.2mm; Temp, op. max:120(degree C); Temp, op. min:-40(degree C); Length / Height, external:9.25mm; Width, RoHS Compliant: Yes
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS2196LN+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC T1 Dual Framer LIU RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS219T 功能描述:烙鐵 DESOLDERING HEAD RoHS:否 制造商:Weller 產(chǎn)品:Soldering Stations 類型:Digital, Iron, Stand, Cleaner 瓦特:50 W 最大溫度:+ 850 F 電纜類型:US Cord Included
DS21E352 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21E352N 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21E354 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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