參數(shù)資料
型號: DS2196LN
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù): 32/157頁
文件大小: 734K
代理商: DS2196LN
DS2196
32 of 157
TCR1A: TRANSMIT CONTROL REGISTER 1 FRAMER A (Address = 35 Hex)
(MSB)
LOTCMC
(LSB)
TYEL
TFPT
TCPT
RBSE
GB7S
TFDLS
TBL
SYMBOL
POSITION
NAME AND DESCRIPTION
LOTCMC
TCR1A.7
Loss Of Transmit Clock Mux Control.
Determines whether
the transmit side of Formatter A should switch to MCLK if the
TCLK input should fail to transition (see Figure 1.1 for details).
0 = do not switch to MCLK if TCLKA stops
1 = switch to MCLK if TCLKA stops
Transmit F–Bit Pass Through.
(see note below)
0 = F bits sourced internally
1 = F bits sampled at TSERA
Transmit CRC Pass Through.
(see note below)
0 = source CRC6 bits internally
1 = CRC6 bits sampled at TSERA during F–bit time
Robbed Bit Signaling Enable.
(see note below)
0 = no signaling is inserted in any channel
1 = signaling is inserted in all channels (the TTR registers can
be used to block insertion on a channel by channel basis)
Global Bit 7 Stuffing.
(see note below)
0 = allow the TTR registers to determine which channels
containing all 0’s are to be Bit 7 stuffed
1 = force Bit 7 stuffing in all zero byte channels regardless of
how the TTR registers are programmed
TFDL Register Select.
(see note below)
0 = source FDL or Fs bits from the internal TFDL register
(legacy FDL support mode)
1 = source FDL or Fs bits from the internal HDLC/BOC
controller or the TLINKA pin
Transmit Blue Alarm.
(see note below)
0 = transmit data normally
1 = transmit an unframed all 1’s code at TPOSOA and
TNEGOA
Transmit Yellow Alarm.
(see note below)
0 = do not transmit yellow alarm
1 = transmit yellow alarm
TFPT
TCR1A.6
TCPT
TCR1A.5
RBSE
TCR1A.4
GB7S
TCR1A.3
TFDLS
TCR1A.2
TBL
TCR1A.1
TYEL
TCR1A.0
NOTE:
For a description of how the bits in TCR1A affect the transmit side formatter, see Figure 21-7.
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