- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379182 > DS2196LN Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 PDF資料下載
參數(shù)資料
| 型號： | DS2196LN |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁數(shù)： | 115/157頁 |
| 文件大?。?/td> | 734K |
| 代理商： | DS2196LN |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁當(dāng)前第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁
DS2196
115 of 157
TDC2A: TRANSMIT HDLC DS0 CONTROL REGISTER 2 FRAMER A
(Address = 93 Hex)
TDC2B: TRANSMIT HDLC DS0 CONTROL REGISTER 2 FRAMER B
(Address = 97 Hex)
(MSB)
TDB8
(LSB)
TDB1
TDB7
TDB6
TDB5
TDB4
TDB3
TDB2
SYMBOL
TDB8
POSITION
TDC2.7
NAME AND DESCRIPTION
DS0 Bit 8 Suppress Enable.
MSB of the DS0. Set to 1 to stop
this bit from being used.
DS0 Bit 7 Suppress Enable.
Set to 1 to stop this bit from
being used.
DS0 Bit 6 Suppress Enable.
Set to 1 to stop this bit from
being used.
DS0 Bit 5 Suppress Enable.
Set to 1 to stop this bit from
being used.
DS0 Bit 4 Suppress Enable.
Set to 1 to stop this bit from
being used.
DS0 Bit 3 Suppress Enable.
Set to 1 to stop this bit from
being used.
DS0 Bit 2 Suppress Enable.
Set to 1 to stop this bit from
being used.
DS0 Bit 1 Suppress Enable.
LSB of the DS0. Set to 1 to stop
this bit from being used.
TDB7
TDC2.6
TDB6
TDC2.5
TDB5
TDC2.4
TDB4
TDC2.3
TDB3
TDC2.2
TDB2
TDC2.1
TDB1
TDC2.0
18.2 LEGACY FDL SUPPORT
18.2.1 Overview
The DS2196 maintains the circuitry that existed in the previous generation of Dallas Semiconductor’s
single chip transceivers and quad framers. Section 18.2 covers the circuitry and operation of this legacy
functionality. In new applications, it is recommended that the HDLC controller and BOC controller
described in Section 18.1 be used. On the receive side, it is possible to have both the new HDLC/BOC
controller and the legacy hardware working at the same time. However this is not possible on the
transmit side since there can be only one source the of the FDL data internal to the device.
18.2.2 Receive Section
In the receive section, the recovered FDL bits or Fs bits are shifted bit–by–bit into the Receive FDL
register (RFDL). Since the RFDL is 8 bits in length, it will fill up every 2 ms (8 times 250 us). The
framer will signal an external microcontroller that the buffer has filled via the SR2.4 bit. If enabled via
IMR2.4, the INT pin will toggle low indicating that the buffer has filled and needs to be read. The user
has 2 ms to read this data before it is lost. If the byte in the RFDL matches either of the bytes
programmed into the RMTCH1 or RMTCH2 registers, then the SR2.2 bit will be set to a 1 and the INT
pin will toggled low if enabled via IMR2.2. This feature allows an external microcontroller to ignore the
FDL or Fs pattern until an important event occurs.
The framer also contains a zero destuffer, which is controlled via the CCR2.0 bit. In both ANSI T1.403
and TR54016, communications on the FDL follows a subset of a LAPD protocol. The LAPD protocol
states that no more than five 1’s should be transmitted in a row so that the data does not resemble an
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS21Q43AT | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| DS21Q43ATN | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| DS21Q44 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| DS21Q44T | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| DS21Q44TN | MICROSWITCH, SPDT, SIM ROLLER LEVER; Current, contact AC:5A; Force, operating:91.75gf; Travel, pre:16.0mm; Centres, fixing LxW:22.2mm; Temp, op. max:120(degree C); Temp, op. min:-40(degree C); Length / Height, external:9.25mm; Width, RoHS Compliant: Yes |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS2196LN+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC T1 Dual Framer LIU RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS219T | 功能描述:烙鐵 DESOLDERING HEAD RoHS:否 制造商:Weller 產(chǎn)品:Soldering Stations 類型:Digital, Iron, Stand, Cleaner 瓦特:50 W 最大溫度:+ 850 F 電纜類型:US Cord Included |
| DS21E352 | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21E352N | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21E354 | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。