參數(shù)資料
型號: DS2196LN+
廠商: Maxim Integrated Products
文件頁數(shù): 68/157頁
文件大?。?/td> 0K
描述: IC FRAMER DUAL T1 LIU 100-LQFP
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 90
控制器類型: T1 調幀器
接口: 并行/串行
電源電壓: 3.135 V ~ 3.465 V
電流 - 電源: 85mA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應商設備封裝: 100-LQFP(14x14)
包裝: 托盤
DS2196
18 of 157
Signal Type:
Output
This digital output will provide either a frame synchronization pulse or the negative half of a bipolar data stream.
The signal is based on what is provided at the TNEGLI input.
Signal Name:
LNRZ
Signal Description:
LIU NRZ Data
Signal Type:
Output
This digital output will provide either a NRZ data stream or the positive half of a bipolar data stream. The signal is
based on what is provided at the TPOSLI input.
Signal Name:
LCLK
Signal Description:
LIU Clock
Signal Type:
Output
This digital output provides the 1.544 MHz transmit LIU clock. The signal is based on what is provided at the
TCLKLI input.
Signal Name:
TNEGLI
Signal Description:
Transmit Negative Data for the LIU
Signal Type:
Input
This digital input is used to pass either the negative half of a bipolar data stream or a frame synchronization pulse
via the jitter attenuator block to the transmit line driver block and the LFSYNC output pin. Data input to this pin is
sampled on the falling edge of TCLKLI. TNEGLI can be internally connected to TNEGOA/TFSYNCA via the
CCR4A.2 control bit.
Signal Name:
TPOSLI
Signal Description:
Transmit Positive Data for the LIU
Signal Type:
Input
This digital input is used to pass either the positive half of a bipolar data stream or a NRZ data stream via the jitter
attenuator block to the transmit line driver block and the LNRZ output pin. Data input to this pin is sampled on the
falling edge of TCLKLI. TPOSLI can be internally connected to TPOSOA/TNRZA via the CCR4A.2 control bit.
Signal Name:
TCLKLI
Signal Description:
Transmit Clock for the LIU
Signal Type:
Input
This digital input is used to pass a 1.544 MHz clock via the jitter attenuator block to the transmit line driver block
and the LCLK output pin. TCLKLI can be internally connected to TCLKOA via the CCR4A.2 control bit.
Signal Name:
WNRZ
Signal Description:
Working NRZ Data
Signal Type:
Input
This digital input is used to pass a NRZ data stream via the Data Source Selection MUX and the jitter attenuator
block to the RPOSLO and RNEGLO output pins. Data input to this pin is sampled on the falling or rising edge of
WCLK.
Signal Name:
WCLK
Signal Description:
Working Clock
Signal Type:
Input
This digital input is used to pass a 1.544 MHz clock via the Data Source Selection MUX and the jitter attenuator
block to the RCLKLO output pin.
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