參數資料
型號: DS2196LN+
廠商: Maxim Integrated Products
文件頁數: 3/157頁
文件大小: 0K
描述: IC FRAMER DUAL T1 LIU 100-LQFP
產品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 90
控制器類型: T1 調幀器
接口: 并行/串行
電源電壓: 3.135 V ~ 3.465 V
電流 - 電源: 85mA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應商設備封裝: 100-LQFP(14x14)
包裝: 托盤
DS2196
100 of 157
Four new registers were added for the enhanced functionality of the HDLC controller; RDC1, RDC2,
TDC1, and TDC2. Note that the BOC controller is functional when the HDLC controller is used for
DS0s. Section 18 contains all of the HDLC and BOC registers and information on FDL/Fs Extraction
and Insertion with and without the HDLC controller.
17.1HDLC FOR DS0S
When using the HDLC controllers for DS0s, the same registers shown in section 18 will be used except
for the TBOC and RBOC registers and bits HCR.7, HSR.7, and HIMR.7.
As a basic guideline for interpreting and sending HDLC messages and BOC messages, the following
sequences can be applied.
Receive a HDLC Message
1. Enable RPS interrupts
2. Wait for interrupt to occur
3. Disable RPS interrupt and enable either RPE, RNE, or RHALF interrupt
4. Read RHIR to obtain REMPTY status
a. If REMPTY=0, then record OBYTE, CBYTE, and POK bits and then read the FIFO
a1. if CBYTE=0 then skip to step 5
a2. if CBYTE=1 then skip to step 7
b. If REMPTY=1, then skip to step 6
5. Repeat step 4
6. Wait for interrupt, skip to step 4
7. If POK=0, then discard whole packet, if POK=1, accept the packet
8. Disable RPE, RNE, or RHALF interrupt, enable RPS interrupt and return to step 1.
Transmit a HDLC Message
1. Make sure HDLC controller is done sending any previous messages and is current sending flags by
checking that the FIFO is empty by reading the TEMPTY status bit in the THIR register
2. Enable either the THALF or TNF interrupt
3. Read THIR to obtain TFULL status
a. If TFULL=0, then write a byte into the FIFO and skip to next step (special case occurs when
the last byte is to be written, in this case set TEOM=1 before writing the byte and then skip to
step 6)
b. If TFULL=1, then skip to step 5
4. Repeat step 3
5. Wait for interrupt, skip to step 3
6. Disable THALF or TNF interrupt and enable TMEND interrupt
7. Wait for an interrupt, then read TUDR status bit to make sure packet was transmitted correctly.
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