參數(shù)資料
型號: DS2196LN+
廠商: Maxim Integrated Products
文件頁數(shù): 150/157頁
文件大?。?/td> 0K
描述: IC FRAMER DUAL T1 LIU 100-LQFP
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 90
控制器類型: T1 調(diào)幀器
接口: 并行/串行
電源電壓: 3.135 V ~ 3.465 V
電流 - 電源: 85mA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應商設備封裝: 100-LQFP(14x14)
包裝: 托盤
DS2196
92 of 157
BIR: BERT INFORMATION REGISTER (Address = 43 Hex)
(Refer to Section 7 for explanation of reading latched register bits)
(MSB)
(LSB)
RA1
RA0
RLOS
BED
BBCO
BEC0
SYNC
SYMBOL
POSITION
NAME AND DESCRIPTION
–BIR.7
Not Assigned. Maybe any value when read.
RA1
BIR.6
Receive All 1’s (RA1). A latched bit which is set when 32
consecutive 1’s are received. Allowed to be cleared once a 0 is
received.
RA0
BIR.5
Receive All Zeros (RA0). A latched bit which is set when 32
consecutive zeros are received. Allowed to be cleared once a 1
is received.
RLOS
BIR.4
Receive Loss Of Synchronization (RLOS). A latched bit
which is set whenever the receive BERT begins searching for a
pattern. Once synchronization is achieved, this bit will remain
set until read.
BED
BIR.3
Bit Error Detected (BED). A latched bit which is set when a
bit error is detected. The receive BERT must be in
synchronization for it detect bit errors. Cleared when read. Can
generate interrupts if enabled via IEBED (BC1.6).
BBCO
BIR.2
BERT Bit Counter Overflow (BBCO). A latched bit which is
set when the 32-bit BERT Bit Counter (BBC) overflows.
Cleared when read and will not be set again until another
overflow occurs. Can generate interrupts if enabled via IEOF
(BC1.5).
BECO
BIR.1
BERT Error Counter Overflow (BECO). A latched bit
which is set when the 24-bit BERT Error Counter (BEC)
overflows. Cleared when read and will not be set again until
another overflow occurs. Can generate interrupts if enabled via
IEOF (BC1.5).
SYNC
BIR.0
Real Time Synchronization Status (SYNC). Real time status
of the synchronizer (this bit is not latched). Will be set when
the incoming pattern matches for 32 consecutive bit positions.
Will be cleared when 6 or more bits out of 64 are received in
error. Can generate interrupts on change of state if enabled via
IESYNC (BC1.7).
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