參數(shù)資料
型號： DS2196LN+
廠商： Maxim Integrated Products
文件頁數(shù)： 22/157頁
文件大小： 0K
描述： IC FRAMER DUAL T1 LIU 100-LQFP
產(chǎn)品培訓模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝： 90
控制器類型： T1 調(diào)幀器
接口： 并行/串行
電源電壓： 3.135 V ~ 3.465 V
電流 - 電源： 85mA
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 100-LQFP
供應商設備封裝： 100-LQFP（14x14）
包裝： 托盤
DS2196
118 of 157
19.
LINE INTERFACE FUNCTION
The line interface function in the DS2196 contains three sections; (1) the receiver which handles clock
and data recovery, (2) the transmitter which wave shapes and drives the T1 line, and (3) the jitter
attenuator. Each of these three sections is controlled by the Line Inter-face Control Register (LICR)
which is described below.
LICR: LINE INTERFACE CONTROL REGISTER FRAMER A
(Address = 7C Hex)
(MSB)
(LSB)
LBOS2
LBOS1
LBOS0
EGL
JAS
JABDS
DJA
TPD
SYMBOL
POSITION
NAME AND DESCRIPTION
LBOS2
LICR.7
Line Build Out Select Bit 2. Sets the transmitter build out; see
the Table 19–1
LBOS1
LICR.6
Line Build Out Select Bit 1. Sets the transmitter build out; see
the Table 19–1
LBOS0
LICR.5
Line Build Out Select Bit 0. Sets the transmitter build out; see
the Table 19–1
EGL
LICR.4
Receive Equalizer Gain Limit.
0 = –36 dB
1 = –15 dB
JAS
LICR.3
Jitter Attenuator Select.
0 = place the jitter attenuator on the receive side
1 = place the jitter attenuator on the transmit side
JABDS
LICR.2
Jitter Attenuator Buffer Depth Select.
0 = 128 bits
1 = 32 bits (use for delay sensitive applications)
DJA
LICR.1
Disable Jitter Attenuator.
0 = jitter attenuator enabled
1 = jitter attenuator disabled
TPD
LICR.0
Transmit Power Down.
0 = normal transmitter operation
1 = powers down the transmitter and 3-states the TTIP and
TRING pins
19.1RECEIVE CLOCK AND DATA RECOVERY
The DS2196 contains a digital clock recovery system. See the DS2196 Block Diagram in Section 1 and
Figure 19–1 for more details. The DS2196 couples to the receive T1 twisted pair via a 1:1 transformer.
See Table 19–2 for transformer details. The 1.544 MHz clock attached at the MCLK pin is internally
multiplied by 16 via an internal PLL and fed to the clock recovery system. The clock recovery system
uses the clock from the PLL circuit to form a 16 times over sampler, which is used to recover the clock
and data. This over sampling technique offers outstanding jitter tolerance (see Figure 19–2).
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DS2196LN+ 功能描述:網(wǎng)絡控制器與處理器 IC T1 Dual Framer LIU RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS219T 功能描述:烙鐵 DESOLDERING HEAD RoHS:否 制造商:Weller 產(chǎn)品:Soldering Stations 類型:Digital, Iron, Stand, Cleaner 瓦特:50 W 最大溫度:+ 850 F 電纜類型:US Cord Included
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