參數資料
型號: DS2152L+
廠商: Maxim Integrated Products
文件頁數: 72/97頁
文件大?。?/td> 0K
描述: IC TXRX T1 1CHIP ENHNCD 100-LQFP
產品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 90
功能: 單芯片收發(fā)器
接口: T1
電路數: 1
電源電壓: 4.75 V ~ 5.25 V
電流 - 電源: 75mA
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應商設備封裝: 100-LQFP(14x14)
包裝: 管件
包括: DSX-1 和 CSU 線路補償發(fā)生器,HDLC 控制器,帶內回路代碼發(fā)生器和檢測器
產品目錄頁面: 1429 (CN2011-ZH PDF)
DS2152
74 of 97
14 TRANSMIT TRANSPARENCY
Each of the 24 T1 channels in the transmit direction of the DS2152 can be either forced to be transparent
or, in other words, can be forced to stop Bit 7 Stuffing and/or Robbed Signaling from overwriting the data
in the channels. Transparency can be invoked on a channel-by-channel basis by properly setting the
TTR1, TTR2, and TTR3 registers.
TTR1/TTR2/TTR3: TRANSMIT TRANSPARENCY REGISTER
(Address = 39 to 3B Hex)
(MSB)
(LSB)
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
TTR1 (39)
CH16
CH15
CH14
CH13
CH12
CH11
CH10
CH9
TTR2 (3A)
CH24
CH23
CH22
CH21
CH20
CH19
CH18
CH17
TTR3 (3B)
SYMBOL
POSITION
NAME AND DESCRIPTION
CH24
TTR3.7
Transmit Transparency Registers.
0 = this DS0 channel is not transparent
CH1
TTR1.0
1 = this DS0 channel is transparent
Each of the bit positions in the Transmit Transparency Registers (TTR1/TTR2/TTR3) represents a DS0
channel in the outgoing frame. When these bits are set to a 1, the corresponding channel is transparent (or
clear). If a DS0 is programmed to be clear, no robbed-bit signaling will be inserted nor will the channel
have Bit 7 stuffing performed. However, in the D4 framing mode, bit 2 will be overwritten by a 0 when a
Yellow Alarm is transmitted. Also, the user has the option to prevent the TTR registers from determining
which channels are to have Bit 7 stuffing performed. If the TCR2.0 and TCR1.3 bits are set to 1, then all
24 T1 channels will have Bit 7 stuffing performed on them regardless of how the TTR registers are
programmed. In this manner, the TTR registers are only affecting which channels are to have robbed-bit
signaling inserted into them. See Figure 16-11 for more details.
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