參數(shù)資料
型號: DS2152L+
廠商: Maxim Integrated Products
文件頁數(shù): 22/97頁
文件大?。?/td> 0K
描述: IC TXRX T1 1CHIP ENHNCD 100-LQFP
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 90
功能: 單芯片收發(fā)器
接口: T1
電路數(shù): 1
電源電壓: 4.75 V ~ 5.25 V
電流 - 電源: 75mA
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應商設備封裝: 100-LQFP(14x14)
包裝: 管件
包括: DSX-1 和 CSU 線路補償發(fā)生器,HDLC 控制器,帶內回路代碼發(fā)生器和檢測器
產(chǎn)品目錄頁面: 1429 (CN2011-ZH PDF)
DS2152
29 of 97
CCR6: COMMON CONTROL REGISTER 6 (Address = 1E Hex)
(MSB)
(LSB)
RJC
RCM4
RCM3
RCM2
RCM1
RCM0
SYMBOL
POSITION
NAME AND DESCRIPTION
RJC
CCR6.7
Receive Japanese CRC6 Enable.
0 = use ANSI/AT&T/ITU CRC6 calculation (normal operation)
1 = use Japanese standard JT-G704 CRC6 calculation
CCR6.6
Not Assigned. Should be set to 0 when written.
CCR6.5
Not Assigned. Should be set to 0 when written.
RCM4
CCR6.4
Receive Channel Monitor Bit 4. MSB of a channel decode that
determines which receive channel data will appear in the
RDS0M register. See Section 7 for details.
RCM3
CCR6.3
Receive Channel Monitor Bit 3.
RCM2
CCR6.2
Receive Channel Monitor Bit 2.
RCM1
CCR6.1
Receive Channel Monitor Bit 1.
RCM0
CCR6.0
Receive Channel Monitor Bit 0. LSB of the channel decode.
CCR7: COMMON CONTROL REGISTER 7 (Address = 0A Hex)
(MSB)
(LSB)
LIRST
RLB
SYMBOL
POSITION
NAME AND DESCRIPTION
LIRST
CCR7.7
Line Interface reset. Setting this bit from a 0 to a 1 will initiate
an internal reset that affects the clock recovery state machine and
jitter attenuator. Normally this bit is only toggled on power-up.
Must be cleared and set again for a subsequent reset.
RLB
CCR7.6
Remote Loopback.
0 = loopback disabled
1 = loopback enabled
CCR7.5 to
CCR7.0
Not Assigned. Should be set to 0 when written to.
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