參數(shù)資料
型號: DS2152L+
廠商: Maxim Integrated Products
文件頁數(shù): 20/97頁
文件大小: 0K
描述: IC TXRX T1 1CHIP ENHNCD 100-LQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 90
功能: 單芯片收發(fā)器
接口: T1
電路數(shù): 1
電源電壓: 4.75 V ~ 5.25 V
電流 - 電源: 75mA
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應(yīng)商設(shè)備封裝: 100-LQFP(14x14)
包裝: 管件
包括: DSX-1 和 CSU 線路補償發(fā)生器,HDLC 控制器,帶內(nèi)回路代碼發(fā)生器和檢測器
產(chǎn)品目錄頁面: 1429 (CN2011-ZH PDF)
DS2152
27 of 97
CCR4: COMMON CONTROL REGISTER 4 (Address = 11 Hex)
(MSB)
(LSB)
RSRE
RPCSI
RFSA1
RFE
RFF
THSE
TPCSI
TIRFS
SYMBOL
POSITION NAME AND DESCRIPTION
RSRE
CCR4.7
Receive Side Signaling Reinsertion Enable. See Section 8.2 for
details.
0 = do not re-insert signaling bits into the data stream presented at the
RSER pin
1 = re-insert the signaling bits into data stream presented at the RSER
pin
RPCSI
CCR4.6
Receive Per-Channel Signaling Insert. See Section 8.2 for more
details.
0 = do not use RCHBLK to determine which channels should have
signaling re-inserted
1 = use RCHBLK to determine which channels should have signaling
re-inserted
RFSA1
CCR4.5
Receive Force Signaling All 1s. See Section 8.2 for more details.
0 = do not force extracted robbed-bit signaling bit positions to a 1
1 = force extracted robbed-bit signaling bit positions to a 1
RFE
CCR4.4
Receive Freeze Enable. See Section 8.2 for details.
0 = no freezing of receive signaling data will occur
1 = allow freezing of receive signaling data at RSIG (and RSER if
CCR4.7 = 1).
RFF
CCR4.3
Receive Force Freeze. Freezes receive side signaling at RSIG (and
RSER if CCR4.7 = 1); will override Receive Freeze Enable (RFE). See
Section 8.2 for details.
0 = do not force a freeze event
1 = force a freeze event
THSE
CCR4.2
Transmit Hardware Signaling Insertion Enable. See Section 8.2 for
details.
0 = do not insert signaling from the TSIG pin into the data stream
presented at the TSER pin
1 = insert the signaling from the TSIG pin into data stream presented at
the TSER pin
TPCSI
CCR4.1
Transmit Per-Channel Signaling Insert. See Section 8.2 for details.
0 = do not use TCHBLK to determine which channels should have
signaling inserted from TSIG
1 = use TCHBLK to determine which channels should have signaling
inserted from TSIG
TIRFS
CCR4.0
Transmit Idle Registers (TIR) Function Select. See Section 9 for
timing details.
0 = TIRs define in which channels to insert idle code
1 = TIRs define in which channels to insert data from RSER (i.e., Per-
Channel Loopback function)
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