參數(shù)資料
型號: DS2152L+
廠商: Maxim Integrated Products
文件頁數(shù): 15/97頁
文件大小: 0K
描述: IC TXRX T1 1CHIP ENHNCD 100-LQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 90
功能: 單芯片收發(fā)器
接口: T1
電路數(shù): 1
電源電壓: 4.75 V ~ 5.25 V
電流 - 電源: 75mA
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應(yīng)商設(shè)備封裝: 100-LQFP(14x14)
包裝: 管件
包括: DSX-1 和 CSU 線路補(bǔ)償發(fā)生器,HDLC 控制器,帶內(nèi)回路代碼發(fā)生器和檢測器
產(chǎn)品目錄頁面: 1429 (CN2011-ZH PDF)
DS2152
22 of 97
TCR2: TRANSMIT CONTROL REGISTER 2 (Address = 36 Hex)
(MSB)
(LSB)
TEST1
TEST0
TZBTSI
TSDW
TSM
TSIO
TD4YM
TB7ZS
SYMBOL
POSITION
NAME AND DESCRIPTION
TEST1
TCR2.7
Test Mode Bit 1 for Output Pins. See Table 4-1.
TEST0
TCR2.6
Test Mode Bit 0 for Output Pins. See Table 4-1.
TZBTSI
TCR2.5
Transmit Side ZBTSI Enable.
0 = ZBTSI disabled
1 = ZBTSI enabled
TSDW
TCR2.4
TSYNC Double-Wide. (Note: this bit must be set to 0 when
TCR2.3 = 1 or when TCR2.2 = 0.)
0 = do not pulse double-wide in signaling frames
1 = do pulse double-wide in signaling frames
TSM
TCR2.3
TSYNC Mode Select.
0 = frame mode (see the timing diagrams in Section 16)
1 = multiframe mode (see the timing diagrams in Section 16)
TSIO
TCR2.2
TSYNC I/O Select.
0 = TSYNC is an input
1 = TSYNC is an output
TD4YM
TCR2.1
Transmit Side D4 Yellow Alarm Select.
0 = 0s in bit 2 of all channels
1 = a 1 in the S-bit position of frame 12
TB7ZS
TCR2.0
Transmit Side Bit 7 Zero Suppression Enable.
0 = no stuffing occurs
1 = Bit 7 force to a 1 in channels with all 0s
Table 4-1. Output Pin Test Modes
TEST 1
TEST 0
EFFECT ON OUTPUT PINS
0
Operate normally
0
1
Force all output pins tri-state (including all I/O pins and parallel port pins)
1
0
Force all output pins low (including all I/O pins except parallel port pins)
1
Force all output pins high (including all I/O pins except parallel port pins)
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