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參數(shù)資料
| 型號(hào)： | DA28F320S5-90 |
| 廠商： | INTEL CORP |
| 元件分類： | DRAM |
| 英文描述： | 16 Characters x 2 Lines, 5x7 Dot Matrix Character and Cursor |
| 中文描述： | 4M X 8 FLASH 5V PROM, 90 ns, PDSO56 |
| 封裝： | 16 X 23.70 MM, SSOP-56 |
| 文件頁(yè)數(shù)： | 51/53頁(yè) |
| 文件大?。?/td> | 641K |
| 代理商： | DA28F320S5-90 |
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E
6.7
INTEL StrataFlash MEMORY TECHNOLOGY, 32 AND 64 MBIT
51
ADVANCE INFORMATION
Block Erase, Program, and Lock-Bit Configuration Performance
(3,4)
#
Sym
Parameter
Notes
2,5
Min
TBD
Typ
(1)
6
Max
TBD
Unit
μs
W16 t
WHQV1
t
EHQV1
W16 t
WHQV2
t
EHQV2
W16 t
WHQV3
t
EHQV3
Write Buffer Byte Program Time
Write Buffer Word Program Time
2,5
TBD
12
TBD
μs
Byte Program Time (Using
Word/Byte Program Command)
Block Program Time (Using Write
to Buffer Command)
Block Erase Time
2
TBD
120
TBD
μs
2
TBD
0.8
TBD
sec
W16 t
WHQV4
t
EHQV4
W16 t
WHQV5
t
EHQV5
W16 t
WHQV6
t
EHQV6
W16 t
WHRH
t
EHRH
NOTES:
1.
Typical values measured at T
= +25 °C and nominal voltages. Assumes corresponding lock-bits are not set. Subject to
change based on device characterization.
2.
Excludes system-level overhead.
3.
These performance numbers are valid for all speed versions.
4.
Sampled but not 100% tested.
5.
These values are valid when the buffer is full, and the start address is aligned on a 32-byte boundary.
2
TBD
1.0
TBD
sec
Set Lock-Bit Time
2
TBD
12
TBD
μs
Clear Block Lock-Bits Time
2
TBD
1.5
TBD
sec
Erase Suspend Latency Time to
Read
25
35
μs
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