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參數(shù)資料
| 型號(hào)： | DA28F320S5-90 |
| 廠商： | INTEL CORP |
| 元件分類(lèi)： | DRAM |
| 英文描述： | 16 Characters x 2 Lines, 5x7 Dot Matrix Character and Cursor |
| 中文描述： | 4M X 8 FLASH 5V PROM, 90 ns, PDSO56 |
| 封裝： | 16 X 23.70 MM, SSOP-56 |
| 文件頁(yè)數(shù)： | 34/53頁(yè) |
| 文件大小： | 641K |
| 代理商： | DA28F320S5-90 |
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INTEL StrataFlash MEMORY TECHNOLOGY, 32 AND 64 MBIT
E
34
ADVANCE INFORMATION
Start
Write Word or Byte
Count, Block Address
Write Buffer Data,
Start Address
X = 0
X = X + 1
Write Next Buffer Data,
Device Address
Abort Buffer Write
Command
Check
X = N
Another Buffer
Write
Read Status Register
SR.7 =
Buffer Write to
Flash Complete
Read Extended
Status Register
XSR.7 =
1
No
Yes
No
No
1
Buffer Write to
Flash Aborted
Yes
No
Yes
Full Status
Check if Desired
Buffer Write to Flash
Confirm D0H
Issue Write Command
E8H, Block Address
Write to Another
Block Address
Write
Buffer Time-Out
0
Set Time-Out
Issue Read
Status Command
Yes
Bus
Operation
Command
Comments
Write
Write to
Buffer
Data = E8H
Block Address
Read
XSR. 7 = Valid
Addr = X
Standby
Check XSR. 7
1 = Write Buffer Available
0 = Write Buffer Not Available
Write
(Note 1, 2)
Data = N = Word/Byte Count
N = 0 Corresponds to Count = 1
Addr = Block Address
Write
(Note 3, 4)
Data = Write Buffer Data
Addr = Device Start Address
Write
(Note 5, 6)
Data = Write Buffer Data
Addr = Device Address
Write
Buffer Write
to Flash
Confirm
Data = D0H
Addr = X
Read
Status Register Data with the
Device Enabled, OE# Low
Updates SR
Addr = X
Standby
Check SR.7
1 = WSM Ready
0 = WSM Busy
1. Byte or word count values on DQ
-DQ
are loaded into the
count register. Count ranges on this device for byte mode are N
= 00H to 1FH and for word mode are N = 0000H to 000FH.
2. The device now outputs the status register when read (XSR is
no longer available).
3. Write Buffer contents will be programmed at the device start
address or destination flash address.
4. Align the start address on a Write Buffer boundary for
maximum programming performance (i.e., A
4
- A
0
of the start
address = 0).
5. The device aborts the Write to Buffer command if the current
address is outside of the original block address.
6. The status register indicates an "improper command
sequence" if the Write to Buffer command is aborted. Follow this
with a Clear Status Register command.
Full status check can be done after all erase and write sequences
complete. Write FFH after the last operation to reset the device to
read array mode.
0
0606_07
Figure 7. Write to Buffer Flowchart
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