參數(shù)資料
型號: DA28F320S5-90
廠商: INTEL CORP
元件分類: DRAM
英文描述: 16 Characters x 2 Lines, 5x7 Dot Matrix Character and Cursor
中文描述: 4M X 8 FLASH 5V PROM, 90 ns, PDSO56
封裝: 16 X 23.70 MM, SSOP-56
文件頁數(shù): 46/53頁
文件大?。?/td> 641K
代理商: DA28F320S5-90
INTEL StrataFlash MEMORY TECHNOLOGY, 32 AND 64 MBIT
E
46
ADVANCE INFORMATION
6.5
AC Characteristics
— Read-Only Operations
(1)
Versions
5 V ± 10% V
CCQ
–120/–150
(4)
(All units in ns unless otherwise noted)
2.7 V—3.6V V
CCQ
–L120/–L150
(4)
#
Sym
Parameter
Notes
Min
Max
Min
Max
R1
t
AVAV
Read/Write Cycle Time
32 Mbit
120
120
64 Mbit
150
150
R2
t
AVQV
Address to Output Delay
32 Mbit
120
120
64 Mbit
150
150
R3
t
ELQV
CE
X
to Output Delay
32 Mbit
2
120
120
64 Mbit
2
150
150
R4
t
GLQV
OE# to Output Delay
2
50
50
R5
t
PHQV
RP# High to Output Delay
32 Mbit
180
180
64 Mbit
210
210
R6
t
ELQX
CE
X
to Output in Low Z
3
0
0
R7
t
GLQX
OE# to Output in Low Z
3
0
0
R8
t
EHQZ
CE
X
High to Output in High Z
3
55
55
R9
t
GHQZ
OE# High to Output in High Z
3
15
15
R10
t
OH
Output Hold from Address, CE
X
, or OE#
Change, Whichever Occurs First
3
0
0
R11
t
ELFL
t
ELFH
CE
X
Low to BYTE# High or Low
3
10
10
R12
t
FLQV
t
FHQV
BYTE# to Output Delay
1000
1000
R13
t
FLQZ
BYTE# to Output in High Z
3
1000
1000
NOTES:
CE
X
low is defined as the first edge of CE
0
, CE
1
, or CE
2
that enables the device. CE
X
high is defined at the first edge of CE
0
,
CE
1
, or CE
2
that disables the device (see Table 2, Chip Enable Truth Table.
1.
See Figure 16, AC Waveform for Read Operationsfor the maximum allowable input slew rate.
2.
OE# may be delayed up to t
-t
after the first edge of CE
0
, CE
1
, or CE
2
that enables the device (see Table 2, Chip
Enable Truth Table without impact on t
ELQV
.
3.
Sampled, not 100% tested.
4.
See Figures 13
–15,
Transient Input/Output Reference Waveform for V
= 5.0 V ±10%,
Transient Input/Output
Reference Waveform for V
CCQ
= 2.7 V –3.6 V,
and
Transient Equivalent Testing Load Circuit
for testing characteristics.
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