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參數(shù)資料
| 型號： | DA28F320S5-90 |
| 廠商： | INTEL CORP |
| 元件分類： | DRAM |
| 英文描述： | 16 Characters x 2 Lines, 5x7 Dot Matrix Character and Cursor |
| 中文描述： | 4M X 8 FLASH 5V PROM, 90 ns, PDSO56 |
| 封裝： | 16 X 23.70 MM, SSOP-56 |
| 文件頁數(shù)： | 41/53頁 |
| 文件大小： | 641K |
| 代理商： | DA28F320S5-90 |
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E
The CUI latches commands issued by system
software and is not altered by V
PEN
, CE
0
, CE
1
, or
CE
2
transitions, or WSM actions. Its state is read
array mode upon power-up, after exit from
reset/power-down mode, or after V
CC
transitions
below V
LKO
. V
CC
must be kept at or above V
PEN
during V
CC
transitions.
INTEL StrataFlash MEMORY TECHNOLOGY, 32 AND 64 MBIT
41
ADVANCE INFORMATION
After block erase, program, or lock-bit configuration,
even after V
PEN
transitions down to V
PENLK
, the CUI
must be placed in read array mode via the Read
Array command if subsequent access to the
memory array is desired. V
PEN
must be kept at or
below V
CC
during V
PEN
transitions.
5.5
Power-Up/Down Protection
The device is designed to offer protection against
accidental block erasure, programming, or lock-bit
configuration during power transitions. Internal
circuitry resets the CUI to read array mode at
power-up.
A system designer must guard against spurious
writes for V
CC
voltages above V
LKO
when V
PEN
is
active. Since WE# must be low and the device
enabled (see Table 2, Chip Enable Truth Table) for
a command write, driving WE# to V
IH
or disabling
the device will inhibit writes. The CUI’s two-step
command sequence architecture provides added
protection against data alteration.
Keeping V
PEN
below V
PENLK
prevents inadvertent
data alteration. In-system block lock and unlock
capability protects the device against inadvertent
programming. The device is disabled while RP# =
V
IL
regardless of its control inputs.
5.6
Power Dissipation
When designing portable systems, designers must
consider battery power consumption not only during
device operation, but also for data retention during
system idle time. Flash memory’s nonvolatility
increases usable battery life because data is
retained when system power is removed.
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