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參數(shù)資料
| 型號： | DA28F320S5-90 |
| 廠商： | INTEL CORP |
| 元件分類： | DRAM |
| 英文描述： | 16 Characters x 2 Lines, 5x7 Dot Matrix Character and Cursor |
| 中文描述： | 4M X 8 FLASH 5V PROM, 90 ns, PDSO56 |
| 封裝： | 16 X 23.70 MM, SSOP-56 |
| 文件頁數(shù)： | 17/53頁 |
| 文件大?。?/td> | 641K |
| 代理商： | DA28F320S5-90 |
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E
NOTES:
1.
Bus operations are defined in Table 3.
2.
X = Any valid address within the device.
BA = Address within the block.
IA = Identifier Code Address: see Figure 6 and Table 13.
QA = Query database Address.
PA = Address of memory location to be programmed.
3.
ID = Data read from Identifier Codes.
QD = Data read from Query database.
SRD = Data read from status register. See Table 16 for a description of the status register bits.
PD = Data to be programmed at location PA. Data is latched on the rising edge of WE#.
CC = Configuration Code.
4.
The upper byte of the data bus (DQ
8
–DQ
15
) during command writes is a “Don’t Care” in x16 operation.
5.
Following the Read Identifier Codes command, read operations access manufacturer, device, block lock, and master lock
codes. See
Read Identifier Codes Command
section for read identifier code data.
6.
If the WSM is running, only DQ
7
is valid; DQ
15
–DQ
8
and DQ
6
–DQ
0
float, which places them in a high-impedance state.
7.
After the Write to Buffer command is issued check the XSR to make sure a buffer is available for writing.
8.
The number of bytes/words to be written to the Write Buffer = N + 1, where N = byte/word count argument. Count ranges
on this device for byte mode are N = 00H to N = 1FH and for word mode are N = 0000H to N = 000FH. The third and
consecutive bus cycles, as determined by N, are for writing data into the Write Buffer. The Confirm command (D0H) is
expected after exactly N + 1 write cycles; any other command at that point in the sequence aborts the write to buffer
operation. Please see Figure 7,
Write to Buffer Flowchart
, for additional information.
9.
The write buffer or erase operation does not begin until a Confirm command (D0h) is issued.
10. If the block is locked, RP# must be at V
HH
to enable block erase or program operations. Attempts to issue a block erase or
program to a locked block while RP# is V
IH
will fail.
11. Either 40H or 10H are recognized by the WSM as the byte/word program setup.
12. If the master lock-bit is set, RP# must be at V
to set a block lock-bit. RP# must be at V
HH
to set the master lock-bit. If the
master lock-bit is not set, a block lock-bit can be set while RP# is V
IH
.
13. If the master lock-bit is set, RP# must be at V
to clear block lock-bits. The clear block lock-bits operation simultaneously
clears all block lock-bits. If the master lock-bit is not set, the Clear Block Lock-Bits command can be done while RP# is V
IH
.
14. Commands other than those shown above are reserved by Intel for future device implementations and should not be used.
15. The Basic Command Set (BCS) is the same as the 28F008SA Command Set or Intel Standard Command Set. The
Scaleable Command Set (SCS) is also referred to as the Intel Extended Command Set.
INTEL StrataFlash MEMORY TECHNOLOGY, 32 AND 64 MBIT
17
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