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參數(shù)資料
| 型號(hào)： | DA28F320S5-90 |
| 廠商： | INTEL CORP |
| 元件分類： | DRAM |
| 英文描述： | 16 Characters x 2 Lines, 5x7 Dot Matrix Character and Cursor |
| 中文描述： | 4M X 8 FLASH 5V PROM, 90 ns, PDSO56 |
| 封裝： | 16 X 23.70 MM, SSOP-56 |
| 文件頁(yè)數(shù)： | 39/53頁(yè) |
| 文件大?。?/td> | 641K |
| 代理商： | DA28F320S5-90 |
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E
INTEL StrataFlash MEMORY TECHNOLOGY, 32 AND 64 MBIT
39
ADVANCE INFORMATION
Start
Write 60H
Write D0H
Read Status Register
SR.7 =
Full Status
Check if Desired
Clear Block Lock-Bits
Complete
FULL STATUS CHECK PROCEDURE
Bus
Operation
Write
Write
Standby
Write FFH after the clear lock-bits operation to place device in read
array mode.
Bus
Operation
Standby
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status
Register command.
If an error is detected, clear the status register before attempting retry
or other error recovery.
1
0
Standby
Command
Clear Block
Lock-Bits Setup
Clear Block or
Lock-Bits Confirm
Comments
Data = 60H
Addr = X
Data = D0H
Addr = X
Check SR.7
1 = WSM Ready
0 = WSM Busy
Command
Comments
Check SR.3
1 = Programming Voltage Error
Detect
Check SR.1
1 = Device Protect RP# = V
IH
,
Read Status Register
Data (See Above)
Voltage Range Error
Device Protect Error
SR.3 =
SR. 1 =
1
0
1
0
Command Sequence
Error
SR.4,5 =
1
0
Clear Block Lock-Bits
Error
SR.5 =
1
0
Read
Status Register Data
Standby
Check SR.4, 5
Both 1 = Command Sequence
Error
Standby
Check SR.5
1 = Clear Block Lock-Bits Error
Clear Block Lock-Bits
Successful
0606_12
Figure 12. Clear Block Lock-Bit Flowchart
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