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參數(shù)資料
| 型號： | DA28F320S5-90 |
| 廠商： | INTEL CORP |
| 元件分類： | DRAM |
| 英文描述： | 16 Characters x 2 Lines, 5x7 Dot Matrix Character and Cursor |
| 中文描述： | 4M X 8 FLASH 5V PROM, 90 ns, PDSO56 |
| 封裝： | 16 X 23.70 MM, SSOP-56 |
| 文件頁數(shù)： | 36/53頁 |
| 文件大小： | 641K |
| 代理商： | DA28F320S5-90 |
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INTEL StrataFlash MEMORY TECHNOLOGY, 32 AND 64 MBIT
E
36
ADVANCE INFORMATION
Erase Block
Time-Out
w
Start
Read
Status Register
SR.7 =
Erase Flash
Block(s) Complete
0
1
No
Full Status
Check if Desired
Suspend Erase
No
Device Supports
Queuing
Issue Block Queue Erase
Command 28H, Block
Address
Read Extended Status
Register
Is Queue
Available
XSR.7=
Another
Block
Erase
Issue Erase Command 28H
Block Address
Read Extended
Status Register
Write Confirm D0H
Block Address
Another
Block
Erase
Is Queue Full
XSR.7=
0=Yes
1=No
Yes
No
1=Yes
Yes
Issue Single Block Erase
Command 20H, Block
Address
No
0=No
No
Suspend
Erase Loop
Yes
Yes
Write Confirm D0H
Block Address
Set Time-Out
Issue Read
Status Command
Q
(
Bus
Operation
Command
Comments
Write
Erase Block
Data = 28H or 20H
Addr = Block Address
XSR.7 = Valid
Addr = X
Check XSR.7
1 = Erase Queue Avail.
0 = No Erase Queue Avail.
Data = 28H
Addr = Block Address
SR.7 = Valid; SR.6 - 0 = X
With the device enabled,
OE# low updates SR
Addr = X
Check XSR.7
1 = Erase Queue Avail.
0 = No Erase Queue Avail.
Data = D0H
Addr = X
Status register data
With the device enabled,
OE# low updates SR
Addr = X
Check SR.7
1 = WSM Ready
0 = WSM Busy
Read
Standby
Write
Erase Block
Read
Standby
Write (Note 1)
Erase
Confirm
Read
Standby
1. The Erase Confirm byte must follow Erase Setup when
the Erase Queue status (XSR.7) = 0.
Full status check can be done after all erase and write
sequences complete. Write FFH after the last operation to
reset the device to read array mode.
Yes
0606_09
Figure 9. Block Erase Flowchart
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