參數(shù)資料
型號(hào)： CYWUSB6934-48LFXC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類(lèi)： 通信及網(wǎng)絡(luò)
英文描述： Multiconductor Cable; Number of Conductors:2; Conductor Size AWG:18; No. Strands x Strand Size:7 x 26; Jacket Material:Polyvinylchloride (PVC); Leaded Process Compatible:Yes; Capacitance:30pF/ft; Conductor Material:Copper RoHS Compliant: Yes
中文描述： SPECIALTY TELECOM CIRCUIT, QCC48
封裝： 7 X 7 MM, LEAD FREE, MO-220, QFN-48
文件頁(yè)數(shù)： 8/30頁(yè)
文件大小： 305K
代理商： CYWUSB6934-48LFXC
CYWUSB6932
CYWUSB6934
Document 38-16007 Rev. *G
Page 8 of 30
Figure 7-1. Revision ID Register
Addr: 0x00
REG_ID
Default: 0x07
7
6
5
4
3
2
1
0
Silicon ID
Product ID
Bit
7:4
3:0
Name
Silicon ID
Product ID
Description
These are the Silicon ID revision bits. 0000 = Rev A, 0001 = Rev B, etc. These bits are read-only.
These are the Product ID revision bits. Fixed at value 0111. These bits are read-only.
Figure 7-2. Control
Addr: 0x03
REG_CONTROL
4
Bypass Internal
Syn Lock Signal
Default: 0x00
7
6
5
3
2
1
0
RX
Enable
TX
Enable
PN Code
Select
Auto Internal
PA
Disable
Internal PA
Enable
Reserved
Reserved
Bit Name
7
RX Enable
Description
The Receive Enable bit is used to place the IC in receive mode.
1 = Receive Enabled
0 = Receive Disabled
The Transmit Enable bit is used to place the IC in transmit mode.
1 = Transmit Enabled
0 = Transmit Disabled
PN Code Select The Pseudo-Noise Code Select bit selects between the upper or lower half of the 64 chips/bit PN code.
1 = 32 Most Significant Bits of PN code are used
0 = 32 Least Significant Bits of PN code are used
This bit applies only when the Code Width bit is set to 32 chips/bit PN codes (Reg 0x04, bit 2=1).
Bypass Internal
Syn Lock Signal
specified in the Syn Lock Count register (Reg 0x38), in units of 2 us. If the internal Syn Lock Signal is used then set
Syn Lock Count to 25 to provide additional assurance that the synthesizer has settled.
1 = Bypass the Internal Syn Lock Signal and wait the amount of time in Syn Lock Count register (Reg 0x38)
0 = Wait for the Syn Lock Signal and then wait the amount of time specified in Syn Lock Count register (Reg 0x38)
It is recommended that the application MCU sets this bit to 1 in order to guarantee a consistent settle time for the
synthesizer.
Auto Internal PA
Disable
options are automatic control by the baseband or by firmware through register writes. For external PA usage, please
see the description of the REG_ANALOG_CTL register (Reg 0x20).
1 = Register controlled Internal PA Enable
0 = Auto controlled Internal PA Enable
When this bit is set to 1, the enabled state of the Internal PA is directly controlled by bit Internal PA Enable (Reg 0x03,
bit 2). It is recommended that this bit is set to 0, leaving
the PA control to the baseband.
Internal PA
Enable
1 = Internal Power Amplifier Enabled
0 = Internal Power Amplifier Disabled
This bit only applies when the Auto Internal PA Disable bit is selected (Reg 0x03, bit 3=1), otherwise this bit is don’t care.
Reserved
This bit is reserved and should be written with a one.
Reserved
This bit is reserved and should be written with a zero.
6
TX Enable
5
4
This bit controls whether the state machine waits for the internal Syn Lock Signal before waiting for the amount of time
3
The Auto Internal PA Disable bit is used to determine the method of controlling the Internal Power Amplifier. The two
2
The Internal PA Enable bit is used to enable or disable the Internal Power Amplifier.
1
0
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