參數(shù)資料
型號(hào): CYWUSB6934-48LFXC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Multiconductor Cable; Number of Conductors:2; Conductor Size AWG:18; No. Strands x Strand Size:7 x 26; Jacket Material:Polyvinylchloride (PVC); Leaded Process Compatible:Yes; Capacitance:30pF/ft; Conductor Material:Copper RoHS Compliant: Yes
中文描述: SPECIALTY TELECOM CIRCUIT, QCC48
封裝: 7 X 7 MM, LEAD FREE, MO-220, QFN-48
文件頁數(shù): 20/30頁
文件大?。?/td> 305K
代理商: CYWUSB6934-48LFXC
CYWUSB6932
CYWUSB6934
Document 38-16007 Rev. *G
Page 20 of 30
Addr: 0x24
REG_CRYSTAL_ADJ
4
Default: 0x00
7
6
5
3
2
1
0
Reserved
Clock Output
Disable
Crystal Adjust
Figure 7-25. Crystal Adjust
Bit
7
6
Name
Reserved
Clock Output
Disable
Description
This bit is reserved and should be written with zero.
The Clock Output Disable bit disables the 13 MHz clock driven on the X13OUT pin.
1 = No 13 MHz clock driven
externa
ll
y
.
0 = 13 MHz
clock
driven
externally
.
If the 13 MHz clock is driven on the X13OUT pin then receive sensitivity will be reduced by -4 dBm on channels
5+13
n
. By default the 13 MHz clock output pin is enabled. This pin is useful for adjusting the 13 MHz clock, but it
interfere with every 13th channel beginning with 2.405GHz channel. Therefore, it is recommended that the 13 MHz
clock output pin be disabled when not in use.
The Crystal Adjust value is used to calibrate the on-chip parallel load capacitance supplied to the crystal. Each
increment of the Crystal Adjust value typically adds 0.135 pF of parallel load capacitance. The total range is 8.5
pF, starting at 8.65 pF. These numbers do not include PCB parasitics, which can add an additional 1-2 pF.
5:0
Crystal Adjust
Addr: 0x26
REG_VCO_CAL
4
Default: 0x00
7
VCO Slope Enable
6
5
3
2
1
0
Reserved
Figure 7-26. VCO Calibration
Bit
7:6
Name
VCO Slope Enable
(Write-Only)
Description
The Voltage Controlled Oscillator (VCO) Slope Enable bits are used to specify the amount of variance automatically
added to the VCO.
11 = -5/+5 VCO adjust. The application MCU must configure this option during initialization.
10 = -2/+3 VCO adjust.
01 = Reserved.
00 = No VCO adjust.
These bits are undefined for read operations.
These bits are reserved and should be written with zeroes.
5:0
Reserved
Addr: 0x2E
REG_PWR_CTL
4
Default: 0x00
7
6
5
3
2
1
0
Reg Power
Control
Reserved
Figure 7-27. Reg Power Control
Bit
7
Name
Reg Power
Control
Reserved
Description
When set, this bit disables unused circuitry and saves radio power. The user must set Reg 0x20, bit 6=1 to enable writes
to Reg 0x2E. The application MCU must set this bit during initialization.
These bits are reserved and should be written with zeroes.
6:0
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