參數(shù)資料
型號(hào)： CYWUSB6934-48LFXC
廠(chǎng)商： CYPRESS SEMICONDUCTOR CORP
元件分類(lèi)： 通信及網(wǎng)絡(luò)
英文描述： Multiconductor Cable; Number of Conductors:2; Conductor Size AWG:18; No. Strands x Strand Size:7 x 26; Jacket Material:Polyvinylchloride (PVC); Leaded Process Compatible:Yes; Capacitance:30pF/ft; Conductor Material:Copper RoHS Compliant: Yes
中文描述： SPECIALTY TELECOM CIRCUIT, QCC48
封裝： 7 X 7 MM, LEAD FREE, MO-220, QFN-48
文件頁(yè)數(shù)： 13/30頁(yè)
文件大?。?/td> 305K
代理商： CYWUSB6934-48LFXC
CYWUSB6932
CYWUSB6934
Document 38-16007 Rev. *G
Page 13 of 30
Addr: 0x09
REG_RX_DATA_A
Default: 0x00
7
6
5
4
3
2
1
0
Data
Figure 7-8. Receive SERDES Data A
Bit
Name
Description
Received Data for Channel A. The over-the-air received order is bit 0 followed by bit 1, followed by bit 2, followed by bit 3,
followed by bit 4, followed by bit 5, followed by bit 6, followed by bit 7. This register is read-only.
7:0
Data
Addr: 0x0A
REG_RX_VALID_A
Default: 0x00
7
6
5
4
3
2
1
0
Valid
Figure 7-9. Receive SERDES Valid A
Bit
Name
Description
These bits indicate which of the bits in the Receive SERDES Data A register (Reg 0x09) are valid. A “1” indicates that the
corresponding data bit is valid for Channel A.
If the Valid Data bit is set in the Receive Interrupt Status register (Reg 0x08) all eight bits in the Receive SERDES Data A register
(Reg 0x0A) are valid. Therefore, it is not necessary to read the Receive SERDES Valid A register (Reg 0x0C). This register is
read-only.
7:0
Valid
Addr: 0x0B
REG_RX_DATA_B
Default: 0x00
7
6
5
4
3
2
1
0
Data
Figure 7-10. Receive SERDES Data B
Bit
Name
Description
Received Data for Channel B. The over-the-air received order is bit 0 followed by bit 1, followed by bit 2, followed by bit 3,
followed by bit 4, followed by bit 5, followed by bit 6, followed by bit 7. This register is read-only.
7:0
Data
Figure 7-11. Receive SERDES Valid B
Addr: 0x0C
REG_RX_VALID_B
Default: 0x00
7
6
5
4
3
2
1
0
Valid
Bit
Name
Description
These bits indicate which of the bits in the Receive SERDES Data B register (Reg 0x0B) are valid. A “1” indicates that the
corresponding data bit is valid for Channel B.
If the Valid Data bit is set in the Receive Interrupt Status register (0x08) all eight bits in the Receive SERDES Data B register
(Reg 0x0B) are valid. Therefore, it is not necessary to read the Receive SERDES Valid B register (Reg 0x0C). This register is
read-only.
7:0
Valid
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