參數(shù)資料
型號: CYWUSB6934-48LFXC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: 通信及網絡
英文描述: Multiconductor Cable; Number of Conductors:2; Conductor Size AWG:18; No. Strands x Strand Size:7 x 26; Jacket Material:Polyvinylchloride (PVC); Leaded Process Compatible:Yes; Capacitance:30pF/ft; Conductor Material:Copper RoHS Compliant: Yes
中文描述: SPECIALTY TELECOM CIRCUIT, QCC48
封裝: 7 X 7 MM, LEAD FREE, MO-220, QFN-48
文件頁數(shù): 15/30頁
文件大?。?/td> 305K
代理商: CYWUSB6934-48LFXC
CYWUSB6932
CYWUSB6934
Document 38-16007 Rev. *G
Page 15 of 30
Note:
5.
All status bits are set and readable in the registers regardless of IRQ enable status. This allows a polling scheme to be implemented without enabling IRQs. The
status bits are affected by the TX Enable and RX Enable (Reg 0x03, bits 7:6). For example, the transmit status will read 0 if the IC is not in transmit mode. These
registers are read-only.
Addr: 0x0E
REG_TX_INT_STAT
Default: 0x00
7
6
5
4
3
2
1
0
Reserved
Underflow
Overflow
Done
Empty
Figure 7-13. Transmit SERDES Interrupt Status
Bit
7:4
3
Name
Reserved
Underflow
Description
These bits are reserved. This register is read-only.
The Underflow bit is used to signal when an underflow condition associated with the Transmit SERDES Data register (Reg
0x0F) has occurred.
1 = Underflow Interrupt pending.
0 = No Underflow Interrupt pending.
This IRQ will assert during an underflow condition to the Transmit SERDES Data register (Reg 0x0F). An underflow occurs
when the transmitter is ready to sample transmit data, but there is no data ready in the Transmit SERDES Data register (Reg
0x0F). This will only assert after the transmitter has transmitted at least one bit. This bit is cleared by reading the Transmit
Interrupt Status register (Reg 0x0E).
The Overflow bit is used to signal when an overflow condition associated with the Transmit SERDES Data register (0x0F)
has occurred.
1 = Overflow Interrupt pending.
0 = No Overflow Interrupt pending.
This IRQ will assert during an overflow condition to the Transmit SERDES Data register (Reg 0x0F). An overflow occurs
when the new data is loaded into the Transmit SERDES Data register (Reg 0x0F) before the previous data has been sent.
This bit is cleared by reading the Transmit Interrupt Status register (Reg 0x0E).
The Done bit is used to signal the end of a data transmission.
1 = Done Interrupt pending.
0 = No Done Interrupt pending.
This IRQ will assert when the data is finished sending a byte of data and there is no more data to be sent. This will only assert
after the transmitter has transmitted as least one bit. This bit is cleared by reading the Transmit Interrupt Status register (Reg
0x0E)
The Empty bit is used to signal when
the Transmit SERDES Data register (Reg 0x0F) has been emptied.
1 = Empty Interrupt pending.
0 = No Empty Interrupt pending.
This IRQ will assert when the transmit serdes is empty. When this IRQ is asserted it is ok to write to the Transmit SERDES
Data register (Reg 0x0F). Writing the Transmit SERDES Data register (Reg 0x0F) will clear this IRQ. It will be set when the
data is loaded into the transmitter, and it is ok to write new data.
2
Overflow
1
Done
0
Empty
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