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參數(shù)資料
| 型號(hào)： | CYV15G0404DXB-BGI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Independent Clock Quad HOTLink II⑩ Transceiver with Reclocker |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA256 |
| 封裝： | 27 X 27 MM, 1.57 MM HEIGHT, TBGA-256 |
| 文件頁數(shù)： | 29/43頁 |
| 文件大小： | 814K |
| 代理商： | CYV15G0404DXB-BGI |
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PRELIMINARY
CYV15G0404DXB
Document #: 38-02097 Rev. **
Page 29 of 43
t
TREFDH
t
RREFDA
t
RREFDW
t
REFxDV–
Transmit Data Hold Time from REFCLKx (TXCKSELx
=
1)
Receive Data Access Time to
REFCLKx (RXCKSELx
=
1)
Receive Data Valid Time Window (RXCKSELx
=
1)
Received Data Valid Time to RXCLK (RXCKSELx
=
1)
0.8
ns
ns
ns
ns
9.7
[26]
10UI-5.8
10UI
[24]
–
5.2
1.5
–0.15
t
REFxDV+
t
REFRX[27]
CYV15G0404DXB Bus Configuration Write Timing Characteristics
Over the Operating Range
t
DATAH
Bus Configuration Data Hold
t
DATAS
Bus Configuration Data Setup
t
WRENP
Bus Configuration WREN Pulse Width
CYV15G0404DXB JTAG Test Clock Characteristics
Over the Operating Range
f
TCLK
JTAG Test Clock Frequency
t
TCLK
JTAG Test Clock Period
CYV15G0404DXB Device RESET Characteristics
Over the Operating Range
t
RST
Device RESET Pulse Width
CYV15G0404DXB Transmit Serial Outputs and TX PLL Characteristics
Over the Operating Range
Parameter
Description
t
B
Bit Time
t
RISE[20]
CML Output Rise Time 20
80% (CML Test Load)
Received Data valid Time from RXCLK (RXCKSELx
=
1)
REFCLKx Frequency Referenced to Received Clock Period
ns
%
+0.15
0
10
10
ns
ns
ns
20
MHz
ns
50
15
ns
Condition
Min.
5128
50
100
180
50
100
180
Max.
660
270
500
1000
270
500
1000
25
11
TBD
200
Unit
ps
ps
ps
ps
ps
ps
ps
ps
ps
SPDSELx = HIGH
SPDSELx = MID
SPDSELx =LOW
SPDSELx = HIGH
SPDSELx = MID
SPDSELx =LOW
IEEE 802.3z
IEEE 802.3z
t
FALL[20]
CML Output Fall Time 80
20% (CML Test Load)
t
DJ [20, 28, 30]
t
RJ[20, 29, 30]
t
REFJ[20]
t
TXLOCK
CYV15G0404DXB Receive Serial Inputs and CDR PLL Characteristics
Over the Operating Range
t
RXLOCK
Receive PLL lock to input data stream (cold start)
Receive PLL lock to input data stream
t
RXUNLOCK
Receive PLL Unlock Rate
t
JTOL[20]
t
DJTOL[20]
Notes:
26. Since this timing parameter is greater than the minimum time period of REFCLK it sets an upper limit to the frequency in which REFCLKx can be used to clock
the receive data out of the output register. For predictable timing, users can use this parameter only if REFCLK period is greater than sum of t
and set-
up time of the upstream device. When this condition is not true, RXCLKx± (a buffered or divided version of REFCLK when RXCKSELx = 1) could be used to
clock the receive data out of the device.
27. REFCLKx± has no phase or frequency relationship with the recovered clock(s) and only acts as a centering reference to reduce clock synchronization time.
REFCLKx± must be within
±
1500 PPM (
±
0.15%) of the transmitter PLL reference (REFCLKx±) frequency. Although transmitting to a HOTLink II receiver
necessitates the frequency difference between the transmitter and receiver reference clocks to be within ±1500-PPM, the stability of the crystal needs to be
within the limits specified by the appropriate standard when transmitting to a remote receiver that is compliant to that standard. For example, to be IEEE 802.3z
Gigabit Ethernet compliant, the frequency stability of the crystal needs to be within ±100 PPM.l.
28. While sending continuous K28.5s, outputs loaded to a balanced 100
load, measured at the cross point of differential outputs, over the operating range.
29. While sending continuous K28.7s, after 100,000 samples measured at the cross point of differential outputs, time referenced to REFCLKx± input, over the
operating range.
30. Total jitter is calculated at an assumed BER of 1E
12. Hence: Total Jitter (t
) = (t
* 14) + t
.
31. Also meets all Jitter Generation and Jitter Tolerance requirements as specified by SMPTE 259, SMPTE 292, ESCON, FICON, Fibre Channel, and DVB-ASI.
Deterministic Jitter (peak-peak)
[31]
Random Jitter (
σ
)
[31]
REFCLKx jitter tolerance / Phase noise limits
Transmit PLLx lock to REFCLKx±
μ
s
376k
376k
46
UI
UI
UI
ps
ps
Total Jitter Tolerance
[31]
Deterministic Jitter Tolerance
[31]
IEEE 802.3z
IEEE 802.3z
600
370
CYV15G0404DXB AC Electrical Characteristics
(continued)
Parameter
Description
Min.
Max
Unit
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYV15G0404DXB-BGXC | 功能描述:電信線路管理 IC 3.3V QUAD HOTLINK II TRANS W/RECLOCKER RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYV15G0404DX-EVAL | 功能描述:界面開發(fā)工具 Quad Indep Ch HOTLink II XCVR RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評(píng)估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| CYV15G0404RB | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Quad HOTLink II⑩ Deserializing Reclocker |
| CYV15G0404RB_07 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Quad HOTLink II⑩ Deserializing Reclocker |
| CYV15G0404RB-BGC | 功能描述:電信線路管理 IC 4x Indep Reclockers COM RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
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