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參數(shù)資料
| 型號： | CYV15G0404DXB-BGI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Independent Clock Quad HOTLink II⑩ Transceiver with Reclocker |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA256 |
| 封裝： | 27 X 27 MM, 1.57 MM HEIGHT, TBGA-256 |
| 文件頁數(shù)： | 2/43頁 |
| 文件大?。?/td> | 814K |
| 代理商： | CYV15G0404DXB-BGI |
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PRELIMINARY
CYV15G0404DXB
Document #: 38-02097 Rev. **
Page 2 of 43
The CYV15G0404DXB satisfies the SMPTE-259M and
SMPTE-292M compliance as per SMPTE EG34-1999 Patho-
logical Test Requirements.
As a second-generation HOTLink device, the CYV15G0404DXB
extends the HOTLink family with enhanced levels of integration
and faster data rates, while maintaining serial-link compatibility
(data, command, and BIST) with other HOTLink devices. The
transmit (TX) section of the CYV15G0404DXB Quad HOTLink II
consists of four independent byte-wide channels. Each channel
can accept either 8-bit data characters or preencoded 10-bit
transmission characters. Data characters may be passed from
the Transmit Input Register to an integrated 8B/10B Encoder
to improve their serial transmission characteristics. These
encoded characters are then serialized and output from dual
Positive ECL (PECL) compatible differential transmission-line
drivers at a bit-rate of either 10- or 20-times the input reference
clock for that channel.
The receive (RX) section of the CYV15G0404DXB Quad
HOTLink II consists of four independent byte-wide channels.
Each channel accepts a serial bit-stream from one of two
PECL-compatible differential line receivers, and using a
completely integrated Clock and Data Recovery PLL, recovers
the timing information necessary for data reconstruction. Each
recovered bit-stream is deserialized and framed into
CYV15G0404DXB Transceiver Logic Block Diagram
characters, 8B/10B decoded, and checked for transmission
errors. Recovered decoded characters are then written to an
internal Elasticity Buffer, and presented to the destination host
system.
The integrated 8B/10B encoder/decoder may be bypassed for
systems that present externally encoded or scrambled data at
the parallel interface.
The parallel I/O interface may be configured for numerous
forms of clocking to provide the highest flexibility in system
architecture. In addition to clocking the transmit path with a
local reference clock, the receive interface may also be
configured to present data relative to a recovered clock or to a
local reference clock.
Each transmit and receive channel contains an independent
BIST pattern generator and checker. This BIST hardware
allows at-speed testing of the high-speed serial data paths in
each transmit and receive section, and across the intercon-
necting links.
The CYV15G0404DXB is ideal for port applications where
different data rates and serial interface standards are
necessary for each channel. Some applications include multi-
format routers and switchers.
x10
Serializer
Phase
Align
Buffer
Encoder
8B/10B
Decoder
8B/10B
x11
Framer
Deserializer
TX
RX
x10
Serializer
Encoder
8B/10B
Decoder
8B/10B
x11
Framer
Deserializer
TX
RX
x10
Serializer
Encoder
8B/10B
Decoder
8B/10B
x11
Framer
Deserializer
TX
RX
x10
Serializer
Encoder
8B/10B
Decoder
8B/10B
x11
Framer
Deserializer
TX
RX
T
R
T
R
T
R
T
R
O
A
±
O
±
I
±
I
±
O
±
O
±
I
±
I
±
O
±
O
±
I
±
I
±
O
±
O
±
I
±
I
±
Phase
Align
Buffer
Phase
Align
Buffer
Phase
Align
Buffer
Elasticity
Buffer
Elasticity
Buffer
Elasticity
Buffer
Elasticity
Buffer
T
R
T
R
T
R
T
R
R
R
R
R
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| CYW2330 | Dual Serial Input PLL with 2.5-GHz and 600-MHz Prescalers |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYV15G0404DXB-BGXC | 功能描述:電信線路管理 IC 3.3V QUAD HOTLINK II TRANS W/RECLOCKER RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYV15G0404DX-EVAL | 功能描述:界面開發(fā)工具 Quad Indep Ch HOTLink II XCVR RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| CYV15G0404RB | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Quad HOTLink II⑩ Deserializing Reclocker |
| CYV15G0404RB_07 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Quad HOTLink II⑩ Deserializing Reclocker |
| CYV15G0404RB-BGC | 功能描述:電信線路管理 IC 4x Indep Reclockers COM RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
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