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| 型號： | CYV15G0404DXB-BGI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Independent Clock Quad HOTLink II⑩ Transceiver with Reclocker |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA256 |
| 封裝： | 27 X 27 MM, 1.57 MM HEIGHT, TBGA-256 |
| 文件頁數(shù)： | 22/43頁 |
| 文件大小： | 814K |
| 代理商： | CYV15G0404DXB-BGI |
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PRELIMINARY
CYV15G0404DXB
Document #: 38-02097 Rev. **
Page 22 of 43
Device Configuration Strategy
The following is a series of ordered events needed to load the
configuration latches on a per channel basis:
1. Pulse RESET Low after device power-up. This operation
resets all four channels.
2. Set the static receiver latch bank for the target channel. May
be performed using a global operation, if the application
permits it. [Optional step if the default settings match the
desired configuration.]
3. Set the static transmitter latch bank for the target channel.
May be performed using a global operation, if the appli-
cation permits it. [Optional step if the default settings match
the desired configuration.]
4. Set the dynamic bank of latches for the target channel.
Enable the Receive PLLs and transmit channels. May be
performed using a global operation, if the application
permits it. [Required step.]
5. Reset the Phase Alignment Buffer for the target channel.
May be performed using a global operation, if the appli-
cation permits it. [Optional if phase align buffer is
bypassed.]
When a receive channel is configured with the decoder
bypassed and the receive clock selected as recovered clock
in half-rate mode (DECBYPx = 0, DECMODEx = 1, RXRATEx
= 0, RXCKSELx = 0), the channel cannot be dynamically
reconfigured to enable the decoder with RXCLKx selected as
the REFCLKx (DECBYPx = 1, RXCKSELx = 1). If such a
change is desired, a global reset should be performed and all
channels should be reconfigured to the desired settings.
RXPLLPDA
RXPLLPDB
RXPLLPDC
RXPLLPDD
RXBISTA
RXBISTB
RXBISTC
RXBISTD
TXBISTA
TXBISTB
TXBISTC
TXBISTD
OE2A
OE2B
OE2C
OE2D
Receive Channel Enable
. The initialization value of the RXPLLPDx latch = 0. RXPLLPDx selects if the
associated receive channel is enabled or powered-down. When RXPLLPDx = 0, the associated PLL and
analog circuitry is powered-down. When RXPLLPDx = 1, the associated PLL and analog circuitry is
enabled.
Receive Bist Disabled
. The initialization value of the RXBISTx latch = 1. RXBISTx selects if receive
BIST is disabled or enabled. When RXBISTx = 1, the receiver BIST function is disabled. When RXBISTx
= 0, the receive BIST function is enabled.
Transmit Bist Disabled
. The initialization value of the TXBISTx latch = 1. TXBISTx selects if the transmit
BIST is disabled or enabled. When TXBISTx = 1, the transmit BIST function is disabled. When
TXBISTx = 0, the transmit BIST function is enabled.
Secondary Differential Serial Data Output Driver Enable
. The initialization value of the OE2x latch =
0. OE2x selects if the OUT2± secondary differential output drivers are enabled or disabled. When OE2x
= 1, the associated serial data output driver is enabled allowing data to be transmitted from the transmit
shifter. When OE2x = 0, the associated serial data output driver is disabled. When a driver is disabled
via the configuration interface, it is internally powered down to reduce device power. If both serial drivers
for a channel are in this disabled state, the associated internal logic for that channel is also powered
down. A device reset (RESET sampled LOW) disables all output drivers.
Primary Differential Serial Data Output Driver Enable
. The initialization value of the OE1x latch = 0.
OE1x selects if the OUT1± primary differential output drivers are enabled or disabled. When OE1x = 1,
the associated serial data output driver is enabled allowing data to be transmitted from the transmit
shifter. When OE1x = 0, the associated serial data output driver is disabled. When a driver is disabled
via the configuration interface, it is internally powered down to reduce device power. If both serial drivers
for a channel are in this disabled state, the associated internal logic for that channel is also powered
down. A device reset (RESET sampled LOW) disables all output drivers.
Transmit Clock Phase Alignment Buffer Reset
. The initialization value of the PABRSTx latch = 1. The
PABRSTx is used to re-center the Transmit Phase Align Buffer. When the configuration latch PABRSTx
is written as a 0, the phase of the TXCLKx input clock relative to its associated REFCLKx+/- is initialized.
PABRST is an asynchronous input, but is sampled by each TXCLKx
↑
to synchronize it to the internal
clock domain. PABRSTx is a self clearing latch. This eliminates the requirement of writing a 1 to complete
the initialization of the Phase Alignment Buffer.
Global Enable
. The initialization value of the GLENx latch = 1. The GLENx is used to reconfigure several
channels simultaneously in applications where several channels may have the same configuration.
When GLENx = 1 for a given address, that address is allowed to participate in a global configuration.
When GLENx = 0 for a given address, that address is disabled from participating in a global configuration.
Force Global Enable
. The initialization value of the FGLENx latch is NA. The FGLENx latch forces a
GLobal ENable no matter what the setting is on the GLENx latch. If FGLENx = 1 for the associated
Global channel, FGLEN forces the global update of the target latch banks.
OE1A
OE1B
OE1C
OE1D
PABRSTA
PABRSTB
PABRSTC
PABRSTD
GLEN[11..0]
FGLEN[2..0]
Table 9. Device Configuration and Control Latch Descriptions
(continued)
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| CYV15G0404DXB-BGXC | 功能描述:電信線路管理 IC 3.3V QUAD HOTLINK II TRANS W/RECLOCKER RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYV15G0404DX-EVAL | 功能描述:界面開發(fā)工具 Quad Indep Ch HOTLink II XCVR RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| CYV15G0404RB | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Quad HOTLink II⑩ Deserializing Reclocker |
| CYV15G0404RB_07 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Quad HOTLink II⑩ Deserializing Reclocker |
| CYV15G0404RB-BGC | 功能描述:電信線路管理 IC 4x Indep Reclockers COM RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
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