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參數(shù)資料
| 型號： | CYV15G0404DXB-BGI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Independent Clock Quad HOTLink II⑩ Transceiver with Reclocker |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA256 |
| 封裝： | 27 X 27 MM, 1.57 MM HEIGHT, TBGA-256 |
| 文件頁數(shù)： | 16/43頁 |
| 文件大?。?/td> | 814K |
| 代理商： | CYV15G0404DXB-BGI |
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PRELIMINARY
CYV15G0404DXB
Document #: 38-02097 Rev. **
Page 16 of 43
The sampling and relock period of the Range Control is calcu-
lated as follows: RANGE_CONTROL_ SAMPLING_PERIOD
= (RECOVERED BYTE CLOCK PERIOD) * (4096).
During the time that the Range Control forces the RXPLL VCO
to track REFCLKx±, the LFIx output is asserted LOW. After a
valid serial data stream is applied, it may take up to one
RANGE CONTROL SAMPLING PERIOD before the PLL
locks to the input data stream, after which LFIx should be
HIGH.
Receive Channel Enabled
The CYV15G0404DXB contains four receive channels that
can be independently enabled and disabled. Each channel
can be enabled or disabled separately through the RXPLLPDx
input latch as controlled by the device configuration interface.
When the RXPLLPDx latch = 0, the associated PLL and
analog circuitry of the channel is disabled. Any disabled
channel indicates a constant link fault condition on the LFIx
output. When RXPLLPDx = 1, the associated PLL and receive
channel is enabled to receive and decode a serial stream.
Note
. When a disabled receive channel is reenabled, the
status of the associated LFIx output and data on the parallel
outputs for the associated channel may be indeterminate for
up to 2 ms.
Clock/Data Recovery
The extraction of a bit-rate clock and recovery of bits from each
received serial stream is performed by a separate CDR block
within each receive channel. The clock extraction function is
performed by an integrated PLL that tracks the frequency of
the transitions in the incoming bit stream and align the phase
of the internal bit-rate clock to the transitions in the selected
serial data stream.
Each CDR accepts a character-rate (bit-rate
÷
10) or half-
character-rate (bit-rate
÷
20) reference clock from the
associated REFCLKx± input. This REFCLKx± input is used to
ensure that the VCO (within the CDR) is operating at the
correct frequency (rather than a harmonic of the bit-rate)
reduce PLL acquisition time
limit unlocked frequency excursions of the CDR VCO when
there is no input data present at the selected Serial Line
Receiver.
Regardless of the type of signal present, the CDR attempts to
recover a data stream from it. If the signalling rate of the
recovered data stream is outside the limits set by the range
control monitors, the CDR tracks REFCLKx± instead of the
data stream. Once the CDR output (RXCLK±) frequency
returns back close to REFCLKx± frequency, the CDR input is
switched back to the input data stream. If no data is present at
the selected line receiver, this switching behavior may result
in brief RXCLK± frequency excursions from REFCLKx±.
However, the validity of the input data stream is indicated by
the LFIx output. The frequency of REFCLKx± is required to be
within ±1500 ppm of the frequency of the clock that drives the
REFCLKx± input of the
remote
transmitter to ensure a lock to
the incoming data stream.
For systems using multiple or redundant connections, the LFIx
output can be used to select an alternate data stream. When
an LFIx indication is detected, external logic can toggle
selection of the associated INx1± and INx2± input through the
associated INSELx input. When a port switch takes place, it is
necessary for the receive PLL for that channel to reacquire the
new serial stream and frame to the incoming character bound-
aries.
Reclocker
The CYV15G0404DXB contains a reclocker mode on each
receive channel which can be independently enabled and
disabled. When the reclocker mode is enabled by RCLKENx,
the received serial data is reclocked and transmitted through
the enabled differential serial outputs of the selected channel.
In the reclocker mode, the RXPLL performs Clock and Data
Recovery functions on the input serial data stream and the
reclocked serial data is routed to the enabled Differential Serial
Outputs. The serial data is also routed to the deserializer and
the deserialized data is presented to the RXDx[7:0] and
RXSTA[2:0] parallel data outputs as configured by DECBYPx.
When the reclocker is enabled, the data on the TXDx[7:0] and
TXCT[1:0] is ignored and not transmitted through the enabled
serial outputs.
Deserializer/Framer
Each CDR circuit extracts bits from the associated serial data
stream and clocks these bits into the Shifter/Framer at the bit-
clock rate. When enabled, the Framer examines the data
stream looking for one or more COMMA or K28.5 characters
at all possible bit positions. The location of this character in the
data stream is used to determine the character boundaries of
all following characters.
Framing Character
The CYV15G0404DXB allows selection of different framing
characters on each channel. Two combinations of framing
characters are supported to meet the requirements of different
interfaces. The selection of the framing character is made
through the FRAMCHARx latches via the configuration
interface.
The specific bit combinations of these framing characters are
listed in
Table 6
. When the specific bit combination of the
selected framing character is detected by the framer, the
boundaries of the characters present in the received data
stream are known.
Framer
The framer on each channel operates in one of three different
modes. Each framer may be enabled or disabled using the
RFENx latches via the configuration interface. When the
framer is disabled (RFENx = 0), no combination of received
bits alters the frame information.
Note:
10. The standard definition of a Comma contains only seven bits. However, since all valid Comma characters within the 8B/10B character set also have the eighth
bit as an inversion of the seventh bit, the compare pattern is extended to a full eight bits to reduce the possibility of a framing error.
Table 6. Framing Character Selector
FRAMCHARx
0
Bits detected in framer
Character Name
COMMA+
COMMA–
-K28.5
+K28.5
Bits Detected
00111110XX
[10]
or 11000001XX
0011111010 or
1100000101
1
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| CYV15G0404DXB-BGXC | 功能描述:電信線路管理 IC 3.3V QUAD HOTLINK II TRANS W/RECLOCKER RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYV15G0404DX-EVAL | 功能描述:界面開發(fā)工具 Quad Indep Ch HOTLink II XCVR RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| CYV15G0404RB | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Quad HOTLink II⑩ Deserializing Reclocker |
| CYV15G0404RB_07 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Quad HOTLink II⑩ Deserializing Reclocker |
| CYV15G0404RB-BGC | 功能描述:電信線路管理 IC 4x Indep Reclockers COM RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
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