- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄256923 > CYDD09S36V18-200BBXC (CYPRESS SEMICONDUCTOR CORP) 128K X 72 DUAL-PORT SRAM, 7.2 ns, PBGA256 PDF資料下載
參數(shù)資料
| 型號(hào)： | CYDD09S36V18-200BBXC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | 128K X 72 DUAL-PORT SRAM, 7.2 ns, PBGA256 |
| 封裝： | 17 X 17 MM, 1 MM PITCH, LEAD FREE, MO-192, FBGA-256 |
| 文件頁數(shù)： | 9/53頁 |
| 文件大?。?/td> | 2422K |
| 代理商： | CYDD09S36V18-200BBXC |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁當(dāng)前第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁
FullFlex
Document #: 38-06072 Rev. *I
Page 17 of 53
Master Reset
The FullFlex family of dual-ports undergo a complete reset
when MRST is asserted. MRST must be driven by VDDIOL
referenced levels. The MRST can be asserted asynchronously
to the clocks and must remain asserted for at least tRS. Once
asserted MRST deasserts READY, initializes the internal burst
counters, internal mirror registers, and internal Busy
Addresses to zero, and initializes the internal mask register to
all “1s”. All mailbox interrupts (INT), Busy Address Outputs
(BUSY), and burst counter interrupts (CNTINT) are
deasserted upon master reset. Additionally, MRST must not
be released until all power supplies including VREF are fully
ramped, all port clocks and mode select inputs (LOWSPD, ZQ,
CQEN, DDRON, FTSEL, and PORTSTD) are valid and stable.
This begins calibration of the DLL and VIM circuits. READY
will be asserted within 1024 clock cycles. READY is a wired
OR capable output with a strong pull-up and weak pull-down.
Up to four outputs may be connected together. For faster
pull-down of the signal, connect a 250-
resistor to VSS. If the
DLL and VIM circuits are disabled for a port, the port will be
operational within five clock cycles. However, the READY will
be asserted within 160 clock cycles.
IEEE 1149.1 Serial Boundary Scan (JTAG)
The FullFlex families incorporate an IEEE 1149.1 serial
boundary scan test access port (TAP). The TAP operates
using JEDEC-standard 3.3V or 2.5V I/O logic levels depending
on the VTTL power supply. It is composed of four input
connections and one output connection required by the test
logic defined by the standard.
Notes:
22. CE is internal signal. CE = LOW if CE0 = LOW and CE1 = HIGH. For a single Read operation, CE only needs to be asserted once at the rising edge of the C and
can be deasserted after that. Data will be out after the following C edge and will be tri-stated after the next C edge.
23. OE is “Don’t Care” for mailbox operation.
24. At least one of BE0, BE1, BE2, BE3, BE4, BE5, BE6, or BE7 must be LOW.
25. The “X” in this diagram represents the counter’s upper bits.
219 218
26
21
25
22
24 23
20
219 218
26
21
25
22
24 23
20
219 218
26
21
25
22
24 23
20
219 218
26
21
25
22
24 23
20
H
L
H
11
0s
1
0
1
0
1
11
00
Xs
0
X
1
X
0
01
11
Xs
1
X
1
X
1
11
00
Xs
0
X
1
X
0
01
Masked Address
Unmasked Address
Mask
Register
LSB
Address
Counter
LSB
CNTINT
Example:
Load
Counter-Mask
Register = 00007F
Load
Address
Counter = 000005
Max
Address
Value
Max + 1
Address
Value
Figure 5. Programmable Counter-Mask Register Operation with WRP deasserted[1,25]
0
27
X
27
X
27
X
27
Function
Left Port
Right Port
R/WL
CEL
A0L–19L
INTL
R/WR
CER
A0R–19R
INTR
Set Right INTR Flag
L
Max. Address
X
L
Reset Right INTR Flag
X
H
L
Max. Address
H
Set Left INTL Flag
X
L
Max. Address–1
X
Reset Left INTL Flag
H
L
Max. Address–1
H
X
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CMUI-67202AL-25 | 1K X 9 OTHER FIFO, 25 ns, PDSO28 |
| CP20840CPGA299B-0C | FPGA, 8400 GATES, CPGA299 |
| CP20840PQFP160B-0C | FPGA, 8400 GATES, PQFP160 |
| CP20840PQFP208B-0C | FPGA, 8400 GATES, PQFP208 |
| CP20840CPGA223A-1C | FPGA, 1685 CLBS, 7100 GATES, CPGA223 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYDD09S72V18-167BBXC | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 9M Sync Dual Port 128Kx72 90nm DDR COM RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CYDD09S72V18-167BBXI | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 9M Sync Dual Port 128Kx72 90nm DDR IND RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CYDD09S72V18-200BBXC | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 9M Sync Dual Port 128Kx72 90nm DDR COM RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CYDD18S18V18-167BBC | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 18M Sync Dual Port 512Kx36 90nm DDR COM RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CYDD18S18V18-167BBXC | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 18M Sync Dual Port 512Kx36 90nm DDR COM RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。