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| 型號： | CYDD09S36V18-200BBXC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | 128K X 72 DUAL-PORT SRAM, 7.2 ns, PBGA256 |
| 封裝： | 17 X 17 MM, 1 MM PITCH, LEAD FREE, MO-192, FBGA-256 |
| 文件頁數(shù)： | 5/53頁 |
| 文件大小： | 2422K |
| 代理商： | CYDD09S36V18-200BBXC |
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FullFlex
Document #: 38-06072 Rev. *I
Page 13 of 53
Variable Impedance Matching (VIM)
Each port contains a Variable Impedance Matching circuit to
set the impedance of the I/O driver to match the impedance of
the on-board traces. The impedance is set for all outputs
except JTAG and is done on a per port basis. To take
advantage of the VIM feature, connect a calibrating resistor
(RQ) that is five times the value of the intended line impedance
from the ZQ pin to VSS. The output impedance is then
adjusted to account for drifts in supply voltage and temper-
ature every 1024 clock cycles. If a port’s clock is suspended,
the VIM circuit will retain its last setting until the clock is
restarted. On restart, it will then resume periodic adjustment.
In the case of a significant change in device temperature or
supply voltage, recalibration will happen every 1024 clock
cycles. A Master Reset will initialize the VIM circuitry. Table 6
shows the VIM parameters and Table 7 describes the VIM
operation modes.
In order to disable VIM, the ZQ pin must be connected to
VDDIO of the relative supply for the I/Os before a Master
Reset.
Address Counter and Mask Register Operations[1]
Each port of the FullFlex families contains a programmable
burst address counter. The burst counter contains four
registers: a counter register, a mask register, a mirror register,
and a busy address register.
The counter register contains the address used to access the
RAM array. It is changed only by the master reset (MRST),
Counter Reset, Counter Load, Retransmit, and Counter
Increment operations.
Table 4. tCCS Timing for All Operating Modes
Port A – Early Arriving Port Port B – Late Arriving Port
tCCS C/C Rise to Opposite C/C Rise Set-up Time
for Non-corrupt Data
Unit
Mode
Active Edge
Mode
Active Edge
SDR
C
SDR
C
tCYC(min) – 0.5
ns
SDR
C
DDR
C
tCYC(min) – 0.5
ns
DDR
C
SDR
C
0.55 * tCYC + tCYC(min) – 1
ns
DDR
C
DDR
C
0.55 * tCYC + tCYC(min) – 1
ns
Table 5. Deterministic Access Control Winning Port
Left Port
Right Port
Clock Timing
BUSYL
BUSYR
Description
Left Clock
Right Clock
Read
X
H
No Collision
Write
Read
>tCCS
0
H
Read OLD Data
0
>tCCS
H
Read NEW Data
<tCCS
0
H
Read OLD Data
H
L
Data Not Guaranteed
0
<tCCS
H
Read NEW Data
H
L
Data Not Guaranteed
Read
Write
>tCCS
0
H
Read NEW Data
0
>tCCS
H
Read OLD Data
<tCCS
0
H
Read NEW Data
L
H
Data Not Guaranteed
0
<tCCS
H
Read OLD Data
L
H
Data Not Guaranteed
Write
0
>–tCCS & <tCCS
L
Array Data Corrupted
0
>tCCS
L
H
Array Stores Right Port Data
>tCCS
0
H
L
Array Stores Left Port Data
Table 6. Variable Impedance Matching Parameters
Parameter
Min.
Max.
Unit
Tolerance
RQ Value
100
275
±2%
Output Impedance
20
55
±15%
Reset Time
N/A
1024
Cycles
N/A
Update Time
N/A
1024
Cycles
N/A
Table 7. Variable Impedance Matching Operation
RQ Connection
Output Configuration
100
–275 to
VSS
Output Driver Impedance = RQ/5 ± 15% at
Vout = VDDIO/2
ZQ to VDDIO
VIM Disabled. Rout < 20
at Vout =
VDDIO/2
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