參數(shù)資料
型號(hào)： CY7C43686AV
廠商： Cypress Semiconductor Corp.
英文描述： 3.3V 16K x36/x18x2 Tri Bus FIFO(3.3V 16K x36/x18x2 三路總線先進(jìn)先出)
中文描述： 3.3 16K的x36/x18x2三總線的FIFO（3.3 16K的x36/x18x2三路總線先進(jìn)先出）
文件頁(yè)數(shù)： 8/39頁(yè)
文件大小： 573K
代理商： CY7C43686AV
CY7C43646AV
CY7C43666AV/CY7C43686AV
8
PRELIMINARY
Switching Characteristics
Over the Operating Range
Parameter
f
S
t
CLK
t
CLKH
t
CLKL
t
DS
Description
7C43646/
66/86AV
-7
7C43646/
66/86AV
-10
7C43646/
66/86AV
-15
Unit
MHz
Min.
Max.
133
Min.
Max.
100
Min.
Max.
67
Clock Frequency, CLKA, CLKB, or CLKC
Clock Cycle Time, CLKA, CLKB, or CLKC
7.5
10
15
ns
Pulse Duration, CLKA, CLKB, or CLKC HIGH
3.5
4
6
ns
Pulse Duration, CLKA, CLKB, or CLKC LOW
Set-Up Time, A
0
–
35
before CLKA
↑
,
B
0
–
17
before CLKB
↑
,
and
C
0
–
17
before CLKC
↑
Set-Up Time, CSA, W/RA, ENA, and MBA before CLKA
↑
;
RENB and MBB before CLKB
↑
,
and WENC and MBC before
CLKC
↑
Set-Up Time, MRS1, MRS2, PRS1, or PRS2 LOW before
CLKA
↑
or CLKB
↑
[7]
Set-Up Time, FS0 and FS1 before MRS1 and MRS2 HIGH
3.5
4
6
ns
3
4
5
ns
t
ENS
3
4
5
ns
t
RSTS
2.5
4
5
ns
t
FSS
t
BES
t
SPMS
t
SDS
t
SENS
t
FWS
t
DH
5
7
7.5
ns
Set-Up Time, BE/FWFT before MRS1 and MRS2 HIGH
5
7
7.5
ns
Set-Up Time, SPM before MRS1 and MRS2 HIGH
Set-Up Time, FS0/SD before CLKA
↑
Set-Up Time, FS1/SEN before CLKA
↑
Set-Up Time, FWFT before CLKA
↑
Hold Time, A
0
–
35
before CLKA
↑
,
B
0
–
17
before CLKB
↑
,
and
C
0
–
17
before CLKC
↑
Hold Time, CSA, W/RA, ENA, and MBA before CLKA
↑
; RENB
and MBB before CLKB
↑
,
and WENC and MBC before CLKC
↑
Hold Time, MRS1, MRS2, PRS1, or PRS2 LOW after CLKA
↑
or CLKB
↑
[7]
Hold Time, FS0 and FS1 after MRS1 and MRS2 HIGH
5
7
7.5
ns
3
4
5
ns
3
4
5
ns
0
0
0
ns
0
0
0
ns
t
ENH
1
2
0
ns
t
RSTH
1
1
4
ns
t
FSH
t
BEH
t
SPMH
t
SDH
t
SENH
t
SPH
t
SKEW1[8]
1
1
2
ns
Hold Time, BE/FWFT after MRS1 and MRS2 HIGH
0
0
2
ns
Hold Time, SPM after MRS1 and MRS2 HIGH
Hold Time, FS0/SD after CLKA
↑
Hold Time, FS1/SEN after CLKA
↑
Hold Time, FS1/SEN HIGH after MRS1 and MRS2 HIGH
Skew Time between CLKA
↑
and CLKB
↑
for EFA/ORA,
EFB/ORB, FFA/IRA, and FFC/IRC
Skew Time between CLKA
↑
and CLKB
↑
for AEA, AEB, AFA,
AFC
Access Time, CLKA
↑
to A
0
–
35
and CLKB
↑
to B
0
–
17
Propagation Delay Time, CLKA
↑
to FFA/IRA and CLKB
↑
to
FFC/IRC
Propagation Delay Time, CLKA
↑
to EFA/ORA and CLKB
↑
to
EFB/ORB
Propagation Delay Time, CLKA
↑
to AEA and CLKB
↑
to AEB
Propagation Delay Time, CLKA
↑
to AFA and CLKC
↑
to AFC
0
0
2
ns
0
1
0
ns
5
5
0
ns
2
2
2
ns
7.5
7.5
7.5
ns
t
SKEW2[8]
7
8
12
ns
t
A
t
WFF
1
6
1
8
3
10
ns
1
6
1
8
2
10
ns
t
REF
1
6
1
8
1
10
ns
t
PAE
t
PAF
Notes:
7.
8.
1
6
1
8
1
10
ns
1
6
1
8
1
10
ns
Requirement to count the clock edge as one of at least four needed to reset a FIFO.
Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between the CLKA cycle and the CLKB
cycle.
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