參數(shù)資料
型號(hào): CY7C43686AV
廠商: Cypress Semiconductor Corp.
英文描述: 3.3V 16K x36/x18x2 Tri Bus FIFO(3.3V 16K x36/x18x2 三路總線先進(jìn)先出)
中文描述: 3.3 16K的x36/x18x2三總線的FIFO(3.3 16K的x36/x18x2三路總線先進(jìn)先出)
文件頁(yè)數(shù): 23/39頁(yè)
文件大小: 573K
代理商: CY7C43686AV
CY7C43646AV
CY7C43666AV/CY7C43686AV
23
PRELIMINARY
Notes:
38. If Port C size is word or byte, IRC is set LOW by the last word or byte write of the long word, respectively.
39. t
is the minimum time between a rising CLKA edge and a rising CLKC edge for IRC to transition HIGH in the next CLKB cycle. If the time between the
rising CLKA edge and rising CLKC edge is less than t
SKEW1
, then the transition of IRC HIGH may occur one CLKC cycle later than shown.
Switching Waveforms
(continued)
t
CLKH
t
CLKL
t
ENS
t
ENH
t
A
LOW
LOW
HIGH
FIFO2 Full
t
ENS
t
ENH
t
WFF
t
WFF
t
CLKH
t
CLKL
t
CLK
t
CLK
t
SKEW1[39]
t
DH
t
DS
t
ENH
t
ENS
Previous Word in FIFO2 Output Register
Next Word From FIFO2
To FIFO2
LOW
CLKA
CSA
W/RA
MBA
ENA
EFA/ORA
A
0
35
CLKC
FFC/IRC
MBC
WENC
C
0
17
IRC Flag Timing and First Available Write when FIFO2 is Full (FWFT Mode)
[38]
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