參數(shù)資料
型號: CY7C43686AV
廠商: Cypress Semiconductor Corp.
英文描述: 3.3V 16K x36/x18x2 Tri Bus FIFO(3.3V 16K x36/x18x2 三路總線先進(jìn)先出)
中文描述: 3.3 16K的x36/x18x2三總線的FIFO(3.3 16K的x36/x18x2三路總線先進(jìn)先出)
文件頁數(shù): 18/39頁
文件大?。?/td> 573K
代理商: CY7C43686AV
CY7C43646AV
CY7C43666AV/CY7C43686AV
18
PRELIMINARY
Notes:
29. If Port B size is word or byte, EFB is set LOW by the last word or byte read from FIFO1, respectively.
30. t
is the minimum time between a rising CLKA edge and a rising CLKB edge for EFB to transition HIGH in the next CLKB cycle. If the time between
the rising CLKA edge and rising CLKB edge is less than t
SKEW1
, then the transition of EFB HIGH may occur one CLKB cycle later than shown.
Switching Waveforms
(continued)
t
CLKH
t
CLKL
t
ENS
t
ENH
t
ENS
t
ENH
t
A
t
DS
W1
LOW
t
DH
HIGH
HIGH
FIFO1 Empty
LOW
LOW
W1
t
ENS
t
ENH
t
REF
t
REF
t
CLKH
t
CLKL
t
CLK
t
CLK
t
SKEW1[30]
CLKA
CSA
W/RA
MBA
ENA
FFA/IRA
A
0
35
CLKB
EFB/ORB
CSB
MBB
RENB
B
0
17
EFB Flag Timing and First Data Read Fall Through when FIFO1 is
Empty (CY Standard Mode)
[29]
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY7C43686AV-7AC 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Triple Depth/Width Tri-Bus 16K x 36/16K x 18 x 2 128-Pin TQFP
CY7C439-40DMB 制造商:Cypress Semiconductor 功能描述:
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