參數(shù)資料
型號: CY7C43686AV
廠商: Cypress Semiconductor Corp.
英文描述: 3.3V 16K x36/x18x2 Tri Bus FIFO(3.3V 16K x36/x18x2 三路總線先進(jìn)先出)
中文描述: 3.3 16K的x36/x18x2三總線的FIFO(3.3 16K的x36/x18x2三路總線先進(jìn)先出)
文件頁數(shù): 19/39頁
文件大?。?/td> 573K
代理商: CY7C43686AV
CY7C43646AV
CY7C43666AV/CY7C43686AV
19
PRELIMINARY
Notes:
31. If Port B size is word or byte, t
is referenced to the rising CLKC edge that writes the last word or byte of the long word, respectively.
32. t
is the minimum time between a rising CLKC edge and a rising CLKA edge for ORA to transition HIGH and to clock the next word to the FIFO2 output
register in three CLKA cycles. If the time between the rising CLKC edge and rising CLKA edge is less than t
SKEW1
, then the transition of ORA HIGH and
load of the first word to the output register may occur one CLKA cycle later than shown.
Switching Waveforms
(continued)
t
CLKH
t
CLKL
t
A
W1
t
DH
HIGH
FIFO2 Empty
LOW
LOW
LOW
Old Data in FIFO2 Output Register
W1
t
ENS
t
ENH
t
REF
t
REF
t
CLKH
t
CLKL
t
CLK
t
SKEW1[32]
t
CLK
t
DS
CLKC
WENC
FFC/IRC
C
0
17
CLKA
EFA/ORA
CSA
W/RA
MBA
ENA
A
0
35
ORA Flag Timing and First Data Word Fall Through when FIFO2 is Empty
[31]
(FWFT Mode)
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參數(shù)描述
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