參數(shù)資料
型號: CY7C43686AV
廠商: Cypress Semiconductor Corp.
英文描述: 3.3V 16K x36/x18x2 Tri Bus FIFO(3.3V 16K x36/x18x2 三路總線先進(jìn)先出)
中文描述: 3.3 16K的x36/x18x2三總線的FIFO(3.3 16K的x36/x18x2三路總線先進(jìn)先出)
文件頁數(shù): 27/39頁
文件大?。?/td> 573K
代理商: CY7C43686AV
CY7C43646AV
CY7C43666AV/CY7C43686AV
27
PRELIMINARY
Note:
54. If Port B is configured for word size, data can be written to the Mail1 register using A
(A
18
35
are don
t care inputs). In this first case B
will have valid
data). If Port B is configured for byte size, data can be written to the Mail1 Register using A
0
8
(A
9
35
are don
t care inputs). In this second case, B
0
8
will
have valid data (B
9
17
will be indeterminate).
Switching Waveforms
(continued)
t
ENH
t
ENS
t
ENH
t
ENS
t
ENH
t
ENS
t
ENH
t
ENS
t
DH
t
DS
W1
t
PMF
t
PMF
t
EN
t
MDV
t
PMR
t
ENS
t
ENH
t
DIS
FIFO1 Output Register
W1 (Remains valid in Mail1 Register after read)
CLKA
CSA
W/RA
MBA
ENA
A
0
35
CLKB
MBF1
CSB
MBB
RENB
Timing for Mail1 Register and MBF1 Flag (CY Standard and FWFT Modes)
[54]
B
0
17
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