參數(shù)資料
型號(hào)： CY7C43686AV
廠商： Cypress Semiconductor Corp.
英文描述： 3.3V 16K x36/x18x2 Tri Bus FIFO(3.3V 16K x36/x18x2 三路總線(xiàn)先進(jìn)先出)
中文描述： 3.3 16K的x36/x18x2三總線(xiàn)的FIFO（3.3 16K的x36/x18x2三路總線(xiàn)先進(jìn)先出）
文件頁(yè)數(shù)： 26/39頁(yè)
文件大小： 573K
代理商： CY7C43686AV
CY7C43646AV
CY7C43666AV/CY7C43686AV
26
PRELIMINARY
Notes:
48. FIFO1 Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 read (CSB = LOW, MBB = LOW). Data in the FIFO1 output register has been read from the
FIFO.
49. D = Maximum FIFO Depth =1K for the CY7C43646AV, 4K for the CY7C43666AV, and 16K for the CY7C43686AV.
50. If Port B size is word or byte, t
is referenced to the rising CLKB edge that writes the last word or byte of the long word, respectively.
51. t
is the minimum time between a rising CLKA edge and a rising CLKB edge for AFA to transition HIGH in the next CLKA cycle. If the time between the
rising CLKA edge and rising CLKB edge is less than t
, then AFA may transition HIGH one CLKB cycle later than shown.
52. If Port C size is word or byte, AFC is set LOW by the last word or byte write of the long word, respectively.
53. t
is the minimum time between a rising CLKC edge and a rising CLKA edge for AFC to transition HIGH in the next CLKC cycle. If the time between
the rising CLKC edge and rising CLKA edge is less than t
SKEW2
, then AFC may transition HIGH one CLKA cycle later than shown.
Switching Waveforms
(continued)
Timing for AFA when FIFO1 is Almost Full (CY Standard and FWFT Modes)
t
PAF
t
ENH
t
ENS
t
PAF
t
ENS
t
ENH
[D
–
(Y1+1)] Words in FIFO1
(D
–
Y1)Words in FIFO1
t
SKEW2[51]
CLKA
ENA
AFA
CLKB
RENB
[48, 49, 50]
t
PAF
t
ENH
t
ENS
t
PAF
t
ENS
t
ENH
[D
–
(Y2+1)] Words in FIFO2
(D
–
Y2)Words in FIFO2
t
SKEW2[53]
CLKC
WENC
AFC
CLKA
ENA
Timing for AFC when FIFO2 is Almost Full (CY Standard and FWFT Modes)
[45, 49, 52]
相關(guān)PDF資料
PDF描述
CY7C453 2Kx9 Cascadable Clocked FIFOs with Programmable Flags(帶可編程標(biāo)記的2Kx9可級(jí)聯(lián)定時(shí)的先進(jìn)先出)
CY7C451 512x9 Cascadable Clocked FIFOs with Programmable Flags(帶可編程標(biāo)記的512x9可級(jí)聯(lián)定時(shí)的先進(jìn)先出)
CY7C454 4Kx9 Cascadable Clocked FIFOs with Programmable Flags(帶可編程標(biāo)記的4Kx9可級(jí)聯(lián)定時(shí)的先進(jìn)先出)
CY7C466A Asynchronous, Cascadable 64K x9 FIFOs(異步，可級(jí)聯(lián)的 64K x9 先進(jìn)先出)
CY7C460A Asynchronous, Cascadable 8K/16K/32K/64K x9 FIFOs
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY7C43686AV-7AC 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Triple Depth/Width Tri-Bus 16K x 36/16K x 18 x 2 128-Pin TQFP
CY7C439-40DMB 制造商:Cypress Semiconductor 功能描述:
CY7C441-14JC 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Width Uni-Dir 512 x 9 32-Pin PLCC
CY7C441-30JC 制造商:Cypress Semiconductor 功能描述:FIFO, 512 x 9, Synchronous, 32 Pin, Plastic, PLCC
CY7C441-30JI 制造商:Rochester Electronics LLC 功能描述:- Bulk
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