參數(shù)資料
型號(hào)： CY7C43686AV
廠商： Cypress Semiconductor Corp.
英文描述： 3.3V 16K x36/x18x2 Tri Bus FIFO(3.3V 16K x36/x18x2 三路總線先進(jìn)先出)
中文描述： 3.3 16K的x36/x18x2三總線的FIFO（3.3 16K的x36/x18x2三路總線先進(jìn)先出）
文件頁(yè)數(shù)： 32/39頁(yè)
文件大?。?/td> 573K
代理商： CY7C43686AV
CY7C43646AV
CY7C43666AV/CY7C43686AV
32
PRELIMINARY
Mailbox Registers
Each FIFO has a 36-bit bypass register to pass command and
control information between Port A and Port B/Port C without
putting it in queue. The Mailbox Select (MBA, MBB, MBC) in-
puts choose between a mail register and a FIFO for a port data
transfer operation. The usable width of both the Mail1 and
Mail2 registers matches the selected bus size for Port C.
A LOW-to-HIGH transition on CLKA writes A
0
35
data to the
Mail1 Register when a Port A write is selected by CSA, W/RA,
and ENA with MBA HIGH.
When sending data from Port C to Port A via the Mail2 Regis-
ter, the following is the case: A LOW-to-HIGH transition on
CLKC writes C
0
17
data to the Mail2 Register when a Port C
write is selected by WENC with MBC HIGH. If the selected
Port C bus size is also 18 bits, then the usable width of the
Mail2 Register employs data lines C
0
–
17
. If the selected Port
C bus size is 9 bits, then the usable width of the Mail2 Register
employs data lines C
0
8
. (In this case, C
9
17
are don
’
t care
inputs.)
Writing data to a mail register sets its corresponding flag
(MBF1 or MBF2) LOW. Attempted writes to a mail register are
ignored while the mail flag is LOW.
When data outputs of a port are active, the data on the bus
comes from the FIFO output register when the port Mailbox
Select input is LOW and from the mail register when the port
Mailbox Select input is HIGH.
The Mail1 Register Flag (MBF1) is set HIGH by a LOW-to-
HIGH transition on CLKB when a Port B read is selected by
CSB, RENB, and ENB with MBB HIGH. For a 18-bit bus size,
18 bits of mailbox data are placed on B
0
–
17
. For a 9-bit bus
size, 9 bits of mailbox data are placed on B
0
–
8
. (In this case,
B
9
–
17
are indeterminate.)
The Mail2 register Flag (MBF2) is set HIGH by a LOW-to-HIGH
transition on CLKA when a Port A read is selected by CSA,
W/RA, and ENA with MBA HIGH.
The data in a mail register remains intact after it is read and
changes only when new data is written to the register. The
Endian Select feature has no effect on the mailbox data.
Bus Sizing
The Port B and Port C buses can be configured in a 18-bit word
or 9-bit byte format for data read from FIFO1 or written to
FIFO2. The levels applied to the Port B Bus Size Select
(SIZEB) and the Port C Bus Size Select (SIZEC) determine
the width of the buses. The bus size can be selected indepen-
dently for Ports B and C. These levels should be static through-
out FIFO operation. Both bus size selections are implemented
at the completion of Master Reset, by the time the Full/Input
Ready flag is set HIGH.
Two different methods for sequencing data transfer are avail-
able for Port B when the bus size selection is either byte-or
word-size. They are referred to as Big Endian (most significant
byte first) and Little Endian (least significant byte first). The
level applied to the Big Endian Select (BE) input during the
LOW-to-HIGH transition of MRS1 and MRS2 selects the endi-
an method that will be active during FIFO operation. BE is a
don
’
t care input when the bus size selected for Port B is long-
word. The endian method is implemented at the completion of
Master Reset, by the time the Full/Input Ready flag is set
HIGH.
Only 36-bit long-word data is written to or read from the two
FIFO memories on the CY7C436X6AV. Bus-matching opera-
tions are done after data is read from the FIFO1 RAM and
before data is written to FIFO2 RAM. These bus-matching op-
erations are not available when transferring data via mailbox
registers. Furthermore, both the word- and byte-size bus se-
lections limit the width of the data bus that can be used for mail
register operations. In this case, only those byte lanes belong-
ing to the selected word- or byte-size bus can carry mailbox
data. The remaining data outputs will be indeterminate. The
remaining data inputs will be don
’
t care inputs. For example,
when a word-size bus is selected, then mailbox data can be
transmitted only between A
0
–
17
and B
0
–
17
. When a byte-size
bus is selected, then mailbox data can be transmitted only be-
tween A
0
–
8
and B
0
–
8
.
Bus-Matching FIFO1 Reads
Data is written to the FIFO1 RAM in 36-bit long-word incre-
ments. If byte or word size is implemented on Port B, only the
first one or two bytes appear on the selected portion of the
FIFO1 output register, with the rest of the long-word stored in
auxiliary registers. In this case, subsequent FIFO1 reads out-
put the rest of the long word to the FIFO1 output register.
When reading data from FIFO1 as byte, the unused B
9
–
17
out-
puts are indeterminate.
Bus-Matching FIFO2 Writes
Data is written to the FIFO2 RAM in 18-bit word increments.
Data written to FIFO2 with a byte or word bus size stores the
initial bytes or words in auxiliary registers. The CLKC rising
edge that writes the word to FIFO2 also stores the entire long-
word in FIFO2 RAM.
When reading data from FIFO2 in byte format, the unused
C
8
–
17
outputs are LOW.
Retransmit (RT1, RT2)
The retransmit feature is beneficial when transferring packets
of data. It enables the receipt of data to be acknowledged by
the receiver and retransmitted if necessary.
The retransmit feature is intended for use when a number of
writes equal to or less than the depth of the FIFO have oc-
curred and at least one word has been read since the last reset
cycle. A LOW pulse on RT1, RT2 resets the internal read point-
er to the first physical location of the FIFO. CLKA and CLKB
may be free running but must be disabled during and t
RTR
after
the retransmit pulse. With every valid read cycle after retrans-
mit, previously accessed data is read and the read pointer is
incremented until it is equal to the write pointer. Flags are gov-
erned by the relative locations of the read and write pointers
and are updated during a retransmit cycle. Data written to the
FIFO after activation of RT1, RT2 are transmitted also. The full
depth of the FIFO can be repeatedly retransmitted.
相關(guān)PDF資料
PDF描述
CY7C453 2Kx9 Cascadable Clocked FIFOs with Programmable Flags(帶可編程標(biāo)記的2Kx9可級(jí)聯(lián)定時(shí)的先進(jìn)先出)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY7C43686AV-7AC 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Triple Depth/Width Tri-Bus 16K x 36/16K x 18 x 2 128-Pin TQFP
CY7C439-40DMB 制造商:Cypress Semiconductor 功能描述:
CY7C441-14JC 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Width Uni-Dir 512 x 9 32-Pin PLCC
CY7C441-30JC 制造商:Cypress Semiconductor 功能描述:FIFO, 512 x 9, Synchronous, 32 Pin, Plastic, PLCC
CY7C441-30JI 制造商:Rochester Electronics LLC 功能描述:- Bulk
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