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參數(shù)資料
| 型號： | CY7C453 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 2Kx9 Cascadable Clocked FIFOs with Programmable Flags(帶可編程標(biāo)記的2Kx9可級聯(lián)定時的先進(jìn)先出) |
| 中文描述： | 2Kx9級聯(lián)與時鐘FIFO的可編程標(biāo)志（帶可編程標(biāo)記的2Kx9可級聯(lián)定時的先進(jìn)先出） |
| 文件頁數(shù)： | 1/23頁 |
| 文件大小： | 437K |
| 代理商： | CY7C453 |
512x9, 2Kx9, and 4Kx9 Cascadable
Clocked FIFOs with Programmable Flags
fax id: 5407
CY7C451
CY7C453
CY7C454
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
December 1989 – Revised January 2, 1997
1CY7C454
Features
High-speed, low-power, first-in first-out (FIFO)
memories
512 x 9 (CY7C451)
2,048 x 9 (CY7C453)
4,096 x 9 (CY7C454)
0.65 micron CMOS for optimum speed/power
High-speed 83-MHz operation (12 ns read/write cycle
time)
Low power — I
CC
=70 mA
Fully asynchronous and simultaneous read and write
operation
Empty, Full, Half Full, and programmable Almost Empty
and Almost Full status flags
TTL compatible
Retransmit function
Parity generation/checking
Output Enable (OE
)
pins
Independent read and write enable pins
Center power and ground pins for reduced noise
Supports free-running 50% duty cycle clock inputs
Width Expansion Capability
Depth Expansion Capability
Available in PLCC packages
Functional Description
The CY7C451, CY7C453, and CY7C454 are high-speed,
low-power, first-in first-out (FIFO) memories with clocked read
and write interfaces. Both FIFOs are 9 bits wide. The
CY7C451 has a 512-word by 9-bit memory array, the
CY7C453 has a 2048-word by 9-bit memory array, and the
CY7C454 has a 4096-word by 9-bit memory array. Devices
can be cascaded to increase FIFO depth. Programmable fea-
tures include Almost Full/Empty flags and generation/checking
of parity. These FIFOs provide solutions for a wide variety of data
buffering needs, including high-speed data acquisition, multiproces-
sor interfaces, and communications buffering.
Both FIFOs have 9-bit input and output ports that are con-
trolled by separate clock and enable signals. The input port is
controlled by a free-running clock (CKW) and a write enable
pin (ENW). When ENW is asserted, data is written into the FIFO on
the rising edge of the CKW signal. While ENW is held active, data is
continually written into the FIFO on each CKW cycle. The output port
is controlled in a similar manner by a free-running read clock (CKR)
and a read enable pin (ENR). The read (CKR) and write (CKW)
clocks may be tied together for single-clock operation or the two
clocks may be run independently for asynchronous read/write appli-
cations. Clock frequencies up to 83.3 MHz are achievable in the stan-
dalone configuration, and up to 83.3 MHz is achievable when FIFOs
are cascaded for depth expansion.
Depth expansion is possible using the cascade input (XI) and
cascade output (XO). The XO signal is connected to the XI of the next
device, and the XO of the last device should be connected to the XI
of the first device. In standalone mode, the input (XI) pin is simply tied
to V
SS
.
In the standalone and width expansion configurations, a LOW
on the retransmit (RT) input causes the FIFOs to retransmit
the data. Read enable (ENR) and the write enable (ENW)
must both be HIGH during the retransmit, and then ENR is
used to access the data.
7C451
7C453
7C454
D
3
Logic Block Diagram
Pin Configurations
C451-1
C451-2
PARITY
OUTTRI–STATE
CREAD
FLAG
CWRITE
WRITE
PREAD
LOGIC
EXLOGIC
RINPUT
PROGRAM
REGISTER
D
0– 8
ENR
CKR
HF
E/F
PAFE/XO
Q
0–7,
Q
8
/PG/PE
ENW
CKW
MR
FL/RT
XI
OE
12
13
31
4
5
6
7
8
9
10
11
3 2 1
30
29
14 15 16 17
26
25
24
23
22
21
Top View
PLCC/LCC
1819 20
27
28
32
FL/RT
MR
V
SS
CKR
ENR
OE
Q
8
/PG/PE
XI
ENW
CKW
V
CC
V
SS
HF
E/F
PAFE/XO
D
0
2RAM
RELOGIC
D
1
D
2
D
4
D
5
D
6
D
7
D
Q
4
Q
1
Q
2
Q
3
Q
5
Q
6
Q
7
Q
0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C451 | 512x9 Cascadable Clocked FIFOs with Programmable Flags(帶可編程標(biāo)記的512x9可級聯(lián)定時的先進(jìn)先出) |
| CY7C454 | 4Kx9 Cascadable Clocked FIFOs with Programmable Flags(帶可編程標(biāo)記的4Kx9可級聯(lián)定時的先進(jìn)先出) |
| CY7C466A | Asynchronous, Cascadable 64K x9 FIFOs(異步，可級聯(lián)的 64K x9 先進(jìn)先出) |
| CY7C460A | Asynchronous, Cascadable 8K/16K/32K/64K x9 FIFOs |
| CY7C460A-10JC | Asynchronous, Cascadable 8K/16K/32K/64K x9 FIFOs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C453 WAF | 制造商:Cypress Semiconductor 功能描述: |
| CY7C453-14JI | 制造商:Cypress Semiconductor 功能描述: |
| CY7C453-20JC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 2K x 9 32-Pin PLCC 制造商:Cypress Semiconductor 功能描述:FIFO, 2K x 9, Synchronous, 32 Pin, Plastic, PLCC |
| CY7C454-14LMB | 制造商:Cypress Semiconductor 功能描述:512X9, 2KX9, AND 4KX9 CASCADABLE CLOCKED FIFOS WITH PROGRAMMABLE |
| CY7C455-14JC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 512 x 18 52-Pin PLCC |
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