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參數(shù)資料
| 型號(hào)： | CY7C453 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 2Kx9 Cascadable Clocked FIFOs with Programmable Flags(帶可編程標(biāo)記的2Kx9可級(jí)聯(lián)定時(shí)的先進(jìn)先出) |
| 中文描述： | 2Kx9級(jí)聯(lián)與時(shí)鐘FIFO的可編程標(biāo)志（帶可編程標(biāo)記的2Kx9可級(jí)聯(lián)定時(shí)的先進(jìn)先出） |
| 文件頁數(shù)： | 16/23頁 |
| 文件大?。?/td> | 437K |
| 代理商： | CY7C453 |
CY7C451
CY7C453
CY7C454
16
PRELIMINARY
Architecture
The CY7C451, CY7C453, and CY7C454 consist of an array
of 512/2048/4096 words of 9 bits each (implemented by an
array of dual-port RAM cells), a read pointer, a write pointer,
control signals (CKR, CKW, ENR, ENW, MR, OE, FL/RT, XI,
XO), and flags (HF, E/F, PAFE).
Resetting the FIFO
Upon power-up, the FIFO must be reset with a Master Reset
(MR) cycle. This causes the FIFO to enter the Empty con-
dition signified by E/F and PAFE being LOW and HF being
HIGH. All data outputs (Q
0
8
) go low at the rising edge of
MR. In order for the FIFO to reset to its default state, a
falling edge must occur on MR and the user must not read
or write while MR is LOW (unless ENR and ENW are HIGH
or unless the device is being programmed). Upon comple-
tion of the Master Reset cycle, all data outputs will go LOW
t
AMR
after MR is deasserted. All flags are guaranteed to be
valid t
MRF
after MR is taken HIGH.
FIFO Operation
When the ENW signal is active (LOW), data present on the
D
0
8
pins is written into the FIFO on each rising edge of
the CKW signal. Similarly, when the ENR signal is active,
data in the FIFO memory will be presented on the Q
0
8
outputs. New data will be presented on each rising edge of
CKR while ENR is active. ENR must be set up t
SEN
before
CKR for it to be a valid read function. ENW must occur t
SEN
before CKW for it to be a valid write function.
An output enable (OE) pin is provided to tri-state the Q
0
8
outputs when OE is not asserted. When OE is enabled,
data in the output register will be available to Q
0
8
outputs
after tOE. If devices are cascaded, the OE function will only
output data on the FIFO that is read enabled.
The FIFO contains overflow circuitry to disallow additional
writes when the FIFO is full, and underflow circuitry to disallow
additional reads when the FIFO is empty. An empty FIFO
maintains the data of the last valid read on its Q
0
8
outputs
even after additional reads occur.
Programming
The CY7C451, CY7C453, and CY7C454 are programmed
during a master reset cycle. If MR and ENW are LOW, a
rising edge on CKW will write D
0
8
inputs into the program-
ming register. MR must be set up a minimum of t
SMRP
be-
fore the program write rising edge and held t
HMRP
after the
program write falling edge. The user has the ability to also
perform a program read during the master reset cycle. This
will occur at the rising edge of CKR when MR and ENR are
asserted. The program read must be performed a minimum
of t
FTP
after a program write, and the program word will be
available t
AP
after the read occurs. If a program write does
not occur, a program read may occur a minimum of t
SMRP
after MR is asserted. This will read the default program
value.
When free-running clocks are tied to CKW and CKR, program-
ming can still occur during a master reset cycle with the adher-
ence to a few additional timing parameters. The enable pins
must be set-up t
SEN
before the rising edge of CKW or CKR.
Hold times of t
HEN
must also be met for ENW and ENR.
Data present on D
0
5
during a program write will determine
the distance from Empty (Full) that the Almost Empty (Al-
most Full) flags will become active. See Table 1 for a
description of the six possible FIFO states. P in 1 refers to
the decimal equivalent of the binary number represented
by D
0
5
. Programming options for the CY7C451 and
CY7C453 are listed in Table 5. Programming resolution is
16 words for either device.
The programmable PAFE function is only valid when the
CY7C451/453/454 are not cascaded. If the user elects not
to program the FIFO’s flags, the default (P=1) is as follows:
Almost Empty condition (Almost Full condition) is activated
when the CY7C451/453/454 contain 16 or less words
(empty locations).
Parity is programmed with the D
6
8
bits. See Table 6 for a
summary of the various parity programming options. Data
present on D
6
8
during a program write will determine
whether the FIFO will generate or check even/odd parity for
the data present on D
0
8
thereafter. If the user elects not
to program the FIFO, the parity function is disabled. Flag
operation and parity are described in greater detail in sub-
sequent sections.
Flag Operation
The CY7C451/453/454 provide three status pins when not
cascaded. The three pins, E/F, PAFE, and HF, allow decod-
ing of six FIFO states (Table 1). PAFE is not available when
FIFOs are cascaded for depth expansion. All flags are syn-
chronous, meaning that the change of states is relative to
one of the clocks (CKR or CKW, as appropriate. See Figure
1). The synchronous architecture guarantees some mini-
mum valid time for the flags. The Empty and Almost Empty
flag states are exclusively updated by each rising edge of
the read clock (CKR). For example, when the FIFO con-
tains 1 word, the next read (rising edge of CKR while
ENR=LOW) causes the flag pins to output a state that rep-
resents Empty. The Half Full, Almost Full, and Full flag
states are updated exclusively by the write clock (CKW).
For example, if the CY7C453 FIFO contains 2047 words
(2048 words indicate Full for the CY7C453), the next write
(rising edge of CKW while ENW=LOW) causes the flag pins
to output a state that is decoded as Full.
]
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PDF描述 |
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| CY7C451 | 512x9 Cascadable Clocked FIFOs with Programmable Flags(帶可編程標(biāo)記的512x9可級(jí)聯(lián)定時(shí)的先進(jìn)先出) |
| CY7C454 | 4Kx9 Cascadable Clocked FIFOs with Programmable Flags(帶可編程標(biāo)記的4Kx9可級(jí)聯(lián)定時(shí)的先進(jìn)先出) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C453 WAF | 制造商:Cypress Semiconductor 功能描述: |
| CY7C453-14JI | 制造商:Cypress Semiconductor 功能描述: |
| CY7C453-20JC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 2K x 9 32-Pin PLCC 制造商:Cypress Semiconductor 功能描述:FIFO, 2K x 9, Synchronous, 32 Pin, Plastic, PLCC |
| CY7C454-14LMB | 制造商:Cypress Semiconductor 功能描述:512X9, 2KX9, AND 4KX9 CASCADABLE CLOCKED FIFOS WITH PROGRAMMABLE |
| CY7C455-14JC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 512 x 18 52-Pin PLCC |
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