參數(shù)資料
型號(hào)： CY7C43666AV
廠商： Cypress Semiconductor Corp.
英文描述： 3.3V 4K x36/x18x2 Tri Bus FIFO(3.3V 4K x36/x18x2 三路總線先進(jìn)先出)
中文描述： 3.3 4K的x36/x18x2三總線的FIFO（3.3 4K的x36/x18x2三路總線先進(jìn)先出）
文件頁(yè)數(shù)： 4/39頁(yè)
文件大?。?/td> 573K
代理商： CY7C43666AV
CY7C43646AV
CY7C43666AV/CY7C43686AV
4
PRELIMINARY
Pin Definitions
Signal Name
Description
I/O
Function
A
0
–
35
AEA
Port A Data
I/O
36-bit bidirectional data port for side A.
Port A Almost
Empty Flag
O
Programmable Almost Empty flag synchronized to CLKA. It is LOW when the number
of words in FIFO2 is less than or equal to the value in the Almost Empty A offset register,
X2.
AEB
Port B Almost
Empty Flag
O
Programmable Almost Empty flag synchronized to CLKB. It is LOW when the number
of words in FIFO1 is less than or equal to the value in the Almost Empty B offset register,
X1.
AFA
Port A Almost
Full Flag
O
Programmable Almost Full flag synchronized to CLKA. It is LOW when the number of
empty locations in FIFO1 is less than or equal to the value in the Almost Full A offset
register, Y1.
AFC
Port C Almost
Full Flag
O
Programmable Almost Full flag synchronized to CLKC. It is LOW when the number of
empty locations in FIFO2 is less than or equal to the value in the Almost Full B offset
register, Y2.
B
0
–
17
BE/FWFT
Port B Data
O
18-bit output data port for port B.
Big Endi-
an/First-Word
Fall-Through
Select
I
This is a dual-purpose pin. During Master Reset, a HIGH on BE will select Big Endian
operation. In this case, depending on the bus size, the most significant byte or word on
Port A is read from Port B first (A-to-B data flow) or written to Port C first (C-to-A data
flow). A LOW on BE will select Little Endian operation. In this case, the least significant
byte or word on Port A is read from Port B first (for A-to-B data flow) or written to Port
C first (C-to-A data flow). After Master Reset, this pin selects the timing mode. A HIGH
on FWFT selects CY Standard Mode, a LOW selects First-Word Fall-Through Mode.
Once the timing mode has been selected, the level on FWFT must be static throughout
device operation.
C
0
–
17
CLKA
Port B Data
I
18-bit input data port for port C.
Port A Clock
I
CLKA is a continuous clock that synchronizes all data transfers through Port A and can
be asynchronous or coincident to CLKB. FFA/IRA, EFA/ORA, AFA, and AEA are all
synchronized to the LOW-to-HIGH transition of CLKA.
CLKB
Port B Clock
I
CLKB is a continuous clock that synchronizes all data transfers through Port B and can
be asynchronous or coincident to CLKA. EFB/ORB and AEB are all synchronized to
the LOW-to-HIGH transition of CLKB.
CLKC
Port C Clock
I
CLKC is a continuous clock that synchronizes all data transfers through Port C and can
be asynchronous or coincident to CLKA. FFC/IRC and AFC are all synchronized to the
LOW-to-HIGH transition of CLKC.
CSA
Port A Chip
Select
I
CSA must be LOW to enable a LOW-to HIGH transition of CLKA to read or write on
Port A. The A
0
–
35
outputs are in the high-impedance state when CSA is HIGH.
CSB must be LOW to enable a LOW-to HIGH transition of CLKB to read or write on
Port B. The B
0
–
17
outputs are in the high-impedance state when CSB is HIGH.
This is a dual-function pin. In the CY Standard Mode, the EFA function is selected. EFA
indicates whether or not the FIFO2 memory is empty. In the FWFT mode, the ORA
function is selected. ORA indicates the presence of valid data on A
0
–
35
outputs, avail-
able for reading. EFA/ORA is synchronized to the LOW-to-HIGH transition of CLKA.
CSB
Port B Chip
Select
I
EFA/ORA
Port A Empty/
Output Ready
Flag
O
EFB/ORB
Port B Empty/
Output Ready
Flag
O
This is a dual-function pin. In the CY Standard Mode, the EFB function is selected. EFB
indicates whether or not the FIFO1 memory is empty. In the FWFT mode, the ORB
function is selected. ORB indicates the presence of valid data on B
0
–
17
outputs, avail-
able for reading. EFB/ORB is synchronized to the LOW-to-HIGH transition of CLKB.
ENA
Port A Enable
I
ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data
on Port A.
ENB
Port B Enable
I
ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data
on Port B.
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PDF描述
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