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參數(shù)資料
| 型號： | CY7C43666AV |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 3.3V 4K x36/x18x2 Tri Bus FIFO(3.3V 4K x36/x18x2 三路總線先進先出) |
| 中文描述： | 3.3 4K的x36/x18x2三總線的FIFO（3.3 4K的x36/x18x2三路總線先進先出） |
| 文件頁數(shù)： | 35/39頁 |
| 文件大?。?/td> | 573K |
| 代理商： | CY7C43666AV |
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CY7C43646AV
CY7C43666AV/CY7C43686AV
35
PRELIMINARY
.
Notes:
60. X1 register holds the offset for AEB; Y1 register holds the offset for AFA.
61. X2 register holds the offset for AEA; Y2 register holds the offset for AFC.
Table 1. Flag Programming
SPM
FS1/SEN
FS0/SD
MRS1
↑
X
↑
X
↑
X
↑
↑
↑
↑
↑
MRS2
X1 and Y1 Registers
[60]
X2 and Y2 Registers
[61]
H
H
H
X
↑
X
↑
X
↑
↑
↑
↑
↑
↑
64
X
H
H
H
X
64
H
H
L
16
X
H
H
L
X
16
H
L
H
8
X
H
L
H
X
8
H
L
L
Parallel programming via Port A
Parallel programming via Port A
L
H
L
Serial programming via SD
Serial programming via SD
L
H
H
Reserved
Reserved
L
L
H
Reserved
Reserved
L
L
L
Reserved
Reserved
Table 2. Port A Enable Function
CSA
H
W/RA
X
ENA
X
MBA
X
CLKA
X
A
0
–
35
Outputs
In high-impedance state
Port Function
None
L
H
L
X
X
↑
↑
X
↑
X
↑
In high-impedance state
None
L
H
H
L
In high-impedance state
FIFO1 write
L
H
H
H
In high-impedance state
Mail1 write
L
L
L
L
Active, FIFO2 output register
None
L
L
H
L
Active, FIFO2 output register
FIFO2 read
L
L
L
H
Active, Mail2 register
None
L
L
H
H
Active, Mail2 register
Mail2 read (set MBF2 HIGH)
Table 3. Port B Enable Function
CSB
H
RENB
X
MBB
X
CLKB
X
B
0
–
17
Outputs
In high-impedance state
Port Function
None
L
H
L
X
↑
X
↑
Active, FIFO1 output register
None
L
H
L
Active, FIFO1 output register
FIFO1 read
L
H
H
Active, Mail1 register
None
L
H
H
Active, Mail1 register
Mail1 read (set MBF1 HIGH)
Table 4. Port C Enable Function
WENC
H
MBC
L
CLKC
↑
↑
X
C
0
–
17
Outputs
In high-impedance state
Port Function
FIFO2 write
H
H
In high-impedance state
Mail2 write
L
L
In high-impedance state
None
L
H
X
Active, Mail1 register
None
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