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參數(shù)資料
| 型號： | CY7C43666AV |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 3.3V 4K x36/x18x2 Tri Bus FIFO(3.3V 4K x36/x18x2 三路總線先進(jìn)先出) |
| 中文描述： | 3.3 4K的x36/x18x2三總線的FIFO（3.3 4K的x36/x18x2三路總線先進(jìn)先出） |
| 文件頁數(shù)： | 13/39頁 |
| 文件大小： | 573K |
| 代理商： | CY7C43666AV |
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CY7C43646AV
CY7C43666AV/CY7C43686AV
13
PRELIMINARY
Notes:
19. CSA=LOW, W/RA=HIGH, MBA=LOW. It is not necessary to program offset register on consecutive clock cycles.
20. t
is the minimum time between the rising CLKA edge and a rising CLKB for FFC/IRC to transition HIGH in the next cycle. If the time between the rising
edge of CLKA and rising edge of CLKC is less than t
, then FFC/IRC may transition HIGH one cycle later than shown.
21. It is not necessary to program offset register bits on consecutive clock cycles. FIFO write attempts are ignored until IRA is set HIGH.
22. t
is the minimum time between the rising CLKA edge and a rising CLKC for FFC/IRC to transition HIGH in the next cycle. If the time between the rising
edge of CLKA and rising edge of CLKC is less than t
, then FFC/IRC may transition HIGH one cycle later than shown.
23. Programmable offsets are written serially to the SD input in the order AFA offset (Y1), AEB offset (X1), AFC offset (Y2), and AEA offset (X2).
Switching Waveforms
(continued)
Parallel Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset
(CY Standard and FWFT Modes)
t
WFF
t
FSS
t
DS
t
FSS
t
FSH
t
FSH
t
ENS
t
ENH
t
DH
t
SKEW1[20]
AFA Offset (Y1)
AFC Offset (Y2)
First Word to FIFO1
CLKA
MRS1, MRS2
SPM
FS1/SEN,
FS0/SD
FFA/IRA
ENA
A
0
35
CLKB
FFC/IRC
[19]
AEB Offset (X1)
AEA Offset (X2)
Serial Programming of the Almost-Full Flag and Almost-Empty Flag
Offset Values (CY Standard and FWFT Modes)
t
FSS
t
SPH
t
SENS
t
SENH
t
SENH
t
SENS
t
SDH
t
SDS
t
SDH
t
SDS
t
SKEW1[22]
t
WFF
AFA Offset (Y1) MSB
t
FSS
t
FSH
t
WFF
CLKA
MRS1, MRS2
SPM
FFA/IRA
FS1/SEN
CLKB
FFA/IRA
[21]
FS0/SD
[23]
AEA Offset (X2) LSB
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C43686AV | 3.3V 16K x36/x18x2 Tri Bus FIFO(3.3V 16K x36/x18x2 三路總線先進(jìn)先出) |
| CY7C453 | 2Kx9 Cascadable Clocked FIFOs with Programmable Flags(帶可編程標(biāo)記的2Kx9可級聯(lián)定時(shí)的先進(jìn)先出) |
| CY7C451 | 512x9 Cascadable Clocked FIFOs with Programmable Flags(帶可編程標(biāo)記的512x9可級聯(lián)定時(shí)的先進(jìn)先出) |
| CY7C454 | 4Kx9 Cascadable Clocked FIFOs with Programmable Flags(帶可編程標(biāo)記的4Kx9可級聯(lián)定時(shí)的先進(jìn)先出) |
| CY7C466A | Asynchronous, Cascadable 64K x9 FIFOs(異步，可級聯(lián)的 64K x9 先進(jìn)先出) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C43682-15AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C43683-10AI | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C43683AV-15AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 16K x 36 128-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:3.3V SYNC FIFO W/BUS MATCHING 16K X36 (NOT IDT COMPAT) - Bulk |
| CY7C43684-10AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C43684AV-10AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Bi-Dir 16K x 36 x 2 128-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:3.3V BIDIR SYNC FIFO W/ BUS MATCHING 16KX32X2 - Bulk |
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