參數(shù)資料
型號: CY7C43666AV
廠商: Cypress Semiconductor Corp.
英文描述: 3.3V 4K x36/x18x2 Tri Bus FIFO(3.3V 4K x36/x18x2 三路總線先進先出)
中文描述: 3.3 4K的x36/x18x2三總線的FIFO(3.3 4K的x36/x18x2三路總線先進先出)
文件頁數(shù): 11/39頁
文件大?。?/td> 573K
代理商: CY7C43666AV
CY7C43646AV
CY7C43666AV/CY7C43686AV
11
PRELIMINARY
Notes:
13. PRS2 and MBC must be HIGH during Master Reset until the rising edge of FFC/IRC goes HIGH.
14. If BE/FWFT is HIGH, then EFA/ORA will go LOW one CLKA cycle earlier than the case where BE/FWFT is LOW.
Switching Waveforms
(continued)
FIFO2 Master Reset Loading X1 and Y1 with a Preset Value of Eight
CLKC
t
RSF
t
RSF
t
RSF
t
WFF
t
FSS
t
FSH
t
SPMS
t
SPMH
t
BES
t
BEH
t
RSTS
t
RSTS
t
FWS
CLKA
MRS2
BE/FWFT
SPM
FS1/SEN,
FS0/SD
FFC/IRC
EFA/ORA
AEB
AFA
MBF2
[13, 14]
t
RSF
t
RSF
相關(guān)PDF資料
PDF描述
CY7C43686AV 3.3V 16K x36/x18x2 Tri Bus FIFO(3.3V 16K x36/x18x2 三路總線先進先出)
CY7C453 2Kx9 Cascadable Clocked FIFOs with Programmable Flags(帶可編程標記的2Kx9可級聯(lián)定時的先進先出)
CY7C451 512x9 Cascadable Clocked FIFOs with Programmable Flags(帶可編程標記的512x9可級聯(lián)定時的先進先出)
CY7C454 4Kx9 Cascadable Clocked FIFOs with Programmable Flags(帶可編程標記的4Kx9可級聯(lián)定時的先進先出)
CY7C466A Asynchronous, Cascadable 64K x9 FIFOs(異步,可級聯(lián)的 64K x9 先進先出)
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