參數(shù)資料
型號: CY7C43666AV
廠商: Cypress Semiconductor Corp.
英文描述: 3.3V 4K x36/x18x2 Tri Bus FIFO(3.3V 4K x36/x18x2 三路總線先進先出)
中文描述: 3.3 4K的x36/x18x2三總線的FIFO(3.3 4K的x36/x18x2三路總線先進先出)
文件頁數(shù): 28/39頁
文件大?。?/td> 573K
代理商: CY7C43666AV
CY7C43646AV
CY7C43666AV/CY7C43686AV
28
PRELIMINARY
Notes:
55. If Port C is configured for word size, data can be written to the Mail2 register using C
. In this first case A
0
17
will have valid data (A
will be
indeterminate). If Port C is configured for byte size, data can be written to the Mail2 Register using B
0
8
(B
9
17
are don
t care inputs). In this second case,
A
will have valid data (A
will be indeterminate).
56. Retransmit is performed in the same manner for FIFO2.
57. Clocks are free running in this case.
58. The flags may change state during Retransmit as a result of the offset of the read and write pointers, but flags will be valid at t
RTR
.
59. For the synchronous PAE and PAF flags (SMODE), an appropriate clock cycle is necessary after t
RTR
to update these flags.
Switching Waveforms
(continued)
t
ENH
t
ENS
t
DH
t
DS
W1
t
PMF
t
PMF
t
EN
t
MDV
t
PMR
t
ENS
t
ENH
t
DIS
FIFO2 Output Register
W1 (Remains valid in Mail2 Register after read)
CLKC
MBC
WENC
C
0
17
CLKA
MBF2
CSA
W/RA
MBA
ENA
A
0
35
Timing for Mail2 Register and MBF2 Flag (CY Standard and FWFT Modes)
[55]
FIFO1 Retransmit Timing
RENB
RT1
t
PRT
t
RTR
EFB/FFA
[56, 57, 58, 59]
相關(guān)PDF資料
PDF描述
CY7C43686AV 3.3V 16K x36/x18x2 Tri Bus FIFO(3.3V 16K x36/x18x2 三路總線先進先出)
CY7C453 2Kx9 Cascadable Clocked FIFOs with Programmable Flags(帶可編程標記的2Kx9可級聯(lián)定時的先進先出)
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