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參數(shù)資料
| 型號(hào)： | CY7C1410AV18_07 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 36-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture |
| 中文描述： | 的36 - Mbit QDR - II型⑩SRAM的2字突發(fā)結(jié)構(gòu) |
| 文件頁(yè)數(shù)： | 9/25頁(yè) |
| 文件大?。?/td> | 1021K |
| 代理商： | CY7C1410AV18_07 |
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CY7C1410AV18
CY7C1425AV18
CY7C1412AV18
CY7C1414AV18
Document #: 38-05615 Rev. *D
Page 9 of 25
Application Example
[1]
Truth Table
[2, 3, 4, 5, 6, 7]
Operation
K
RPS
WPS
DQ
DQ
Write Cycle:
Load address on the rising edge of K clock; input
write data on K and K rising edges.
L-H
X
L
D(A + 0) at K(t)
↑
D(A + 1) at K(t)
↑
Read Cycle:
Load address on the rising edge of K clock; wait one
and a half cycle; read data on C and C rising edges.
L-H
L
X
Q(A + 0) at C(t + 1)
↑
Q(A + 1) at C(t + 2)
↑
NOP: No Operation
L-H
H
H
D = X
Q = High-Z
D = X
Q = High-Z
Standby: Clock Stopped
Stopped
X
X
Previous State
Previous State
Write Cycle Descriptions
(CY7C1410AV18 and CY7C1412AV18)
[2, 8]
BWS
0
/
NWS
0
BWS
1
/
NWS
1
K
K
Comments
L
L
L-H
–
During the data portion of a write sequence
:
CY7C1410AV18
both nibbles (D
[7:0]
) are written into the device,
CY7C1412AV18
both bytes (D
[17:0]
) are written into the device.
During the data portion of a write sequence
:
CY7C1410AV18
both nibbles (D
[7:0]
) are written into the device,
CY7C1412AV18
both bytes (D
[17:0]
) are written into the device.
During the data portion of a write sequence
:
CY7C1410AV18
only the lower nibble (D
[3:0]
) is written into the device. D
[7:4]
remains unaltered,
CY7C1412AV18
only the lower byte (D
[8:0]
) is written into the device. D
[17:9]
remains unaltered.
L
L
–
L-H
L
H
L-H
–
Notes:
1. The above application shows four QDR-II being used.
2. X = “Don't Care,” H = Logic HIGH, L= Logic LOW,
represents rising edge.
3. Device powers up deselected and the outputs in a tri-state condition.
4. “A” represents address location latched by the devices when transaction was initiated. A + 00, A + 01 represents the internal address sequence in the burst.
5. “t” represents the cycle at which a Read/Write operation is started. t + 1 and t + 2 are the first and second clock cycles respectively succeeding the “t” clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
7. It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line
charging symmetrically.
8. Assumes a Write cycle was initiated according to the Write Port Cycle Description Truth Table. NWS
0
, NWS
1
, BWS
0
, BWS
1
, BWS
2
and BWS
3
can be altered
on different portions of a Write cycle, as long as the setup and hold requirements are achieved.
C
C#
D
A
K
C
C#
D
A
K
BUS
MASTER
(CPU
or
ASIC)
SRAM #1
SRAM #4
DATA IN
DATA OUT
Address
RPS#
WPS#
BWS#
Source K
Source K#
Delayed K
Delayed K#
R = 50
οημσ
R = 250
οημσ
R = 250
οημσ
R
P
S
#
W
P
S
#
B
W
S
#
R
P
S
#
W
P
S
#
B
W
S
#
Vt
Vt
Vt
R
R
R
ZQ
CQ/CQ#
Q
K#
ZQ
CQ/CQ#
Q
K#
CLKIN/CLKIN#
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