參數(shù)資料
型號(hào)： CY7C1410AV18_07
廠商： Cypress Semiconductor Corp.
英文描述： 36-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture
中文描述： 的36 - Mbit QDR - II型⑩SRAM的2字突發(fā)結(jié)構(gòu)
文件頁(yè)數(shù)： 19/25頁(yè)
文件大小： 1021K
代理商： CY7C1410AV18_07
CY7C1410AV18
CY7C1425AV18
CY7C1412AV18
CY7C1414AV18
Document #: 38-05615 Rev. *D
Page 19 of 25
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied...........................................––55°C to +125°C
Supply Voltage on V
DD
Relative to GND........–0.5V to +2.9V
Supply Voltage on V
DDQ
Relative to GND ......–0.5V to +V
DD
DC Voltage Applied to Outputs
in High-Z State.................................... –0.5V to V
DDQ
+ 0.3V
DC Input Voltage
[18]
...............................–0.5V to V
DD
+ 0.3V
Current into Outputs (LOW).........................................20 mA
Static Discharge Voltage.......................................... > 2001V
(MIL-STD-883, Method 3015)
Latch up Current.................................................... > 200 mA
Capacitance
[21]
Operating Range
Range
Com’l
Ind’l
Ambient
Temperature (T
A
)
0°C to +70°C
–40°C to +85°C
V
DD
[19]
1.8
±
0.1V
V
DDQ
[19]
1.4V to V
DD
Electrical Characteristics
Over the Operating Range
[15, 19]
DC Electrical Characteristics
Over the Operating Range
Parameter
Description
V
DD
Power Supply Voltage
V
DDQ
IO Supply Voltage
V
OH
Output HIGH Voltage
V
OL
Output LOW Voltage
V
OH(LOW)
Output HIGH Voltage
V
OL(LOW)
Output LOW Voltage
V
IH
V
IL
I
X
Input Leakage Current
I
OZ
Output Leakage Current
V
REF
I
DD
V
DD
Operating Supply
Test Conditions
Min
1.7
1.4
Typ
1.8
1.5
Max
1.9
V
DD
Unit
V
V
V
V
V
V
V
V
μ
A
μ
A
V
mA
mA
mA
mA
mA
mA
Note 16
Note 17
I
OH
=
0.1 mA, Nominal Impedance
I
OL
= 0.1 mA, Nominal Impedance
V
DDQ
/2 – 0.12
V
DDQ
/2 – 0.12
V
DDQ
– 0.2
V
SS
V
REF
+ 0.1
–0.3
5
5
0.68
V
DDQ
/2 + 0.12
V
DDQ
/2 + 0.12
V
DDQ
0.2
V
DDQ
+0.3
V
REF
– 0.1
5
5
0.95
740
870
1065
270
300
350
Input HIGH Voltage
[18]
Input LOW Voltage
[18]
GND
≤
V
I
≤
V
DDQ
GND
≤
V
I
≤
V
DDQ,
Output Disabled
Input Reference Voltage
[20]
Typical Value = 0.75V
0.75
V
DD
= Max., I
OUT
= 0
mA, f = f
MAX
= 1/t
CYC
167 MHz
200 MHz
250 MHz
167 MHz
200 MHz
250 MHz
I
SB1
Automatic Power down
Current
Max. V
DD
, Both Ports
Deselected, V
IN
≥
V
IH
or V
IN
≤
V
IL
, f = f
MAX
=
1/t
CYC,
Inputs Static
AC Input Requirements
Over the Operating Range
Parameter
Description
V
IH
Input High (Logic 1) Voltage
V
IL
Input Low (Logic 0) Voltage
Test Conditions
Min
Typ
–
–
Max
–
Unit
V
V
V
REF
+ 0.2
–
V
REF
– 0.2
Parameter
C
IN
C
CLK
C
O
Notes:
15.All voltage referenced to Ground.
16.Output are impedance controlled. I
OH
= –(V
DDQ
/2)/(RQ/5) for values of 175
<= RQ <= 350
s.
17.Output are impedance controlled. I
= (V
/2)/(RQ/5) for values of 175
<= RQ <= 350
.
18.Overshoot: V
(AC) < V
+0.85V (Pulse width less than t
/2), Undershoot: V
(AC) > –1.5V (Pulse width less than t
CYC
/2).
19.Power up: Assumes a linear ramp from 0V to V
(min.) within 200 ms. During this time V
< V
and V
< V
DD
.
20.V
(Min.) = 0.68V or 0.46V
, whichever is larger, V
(Max.) = 0.95V or 0.54V
, whichever is smaller.
21.Tested initially and after any design or process change that may affect these parameters.
Description
Test Conditions
Max
5
4
5
Unit
pF
pF
pF
Input Capacitance
Clock Input Capacitance
Output Capacitance
T
A
= 25
°
C, f = 1 MHz,
V
DD
= 1.8V
V
DDQ
= 1.5V
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