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參數(shù)資料
| 型號(hào)： | CY7C1410AV18_07 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 36-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture |
| 中文描述： | 的36 - Mbit QDR - II型⑩SRAM的2字突發(fā)結(jié)構(gòu) |
| 文件頁(yè)數(shù)： | 21/25頁(yè) |
| 文件大?。?/td> | 1021K |
| 代理商： | CY7C1410AV18_07 |
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CY7C1410AV18
CY7C1425AV18
CY7C1412AV18
CY7C1414AV18
Document #: 38-05615 Rev. *D
Page 21 of 25
Switching Characteristics
Over the Operating Range
[22, 23]
Cypress
Parameter
Consortium
Parameter
Description
250 MHz
200 MHz
167 MHz
Unit
Min
Max
Min
Max
Min
Max
t
POWER
t
CYC
t
KH
t
KL
t
KHKH
V
DD
(Typical) to the first Access
[26]
K Clock and C Clock Cycle Time
1
1
1
ms
t
KHKH
t
KHKL
t
KLKH
t
KHKH
4.0
6.3
5.0
7.9
6.0
8.4
ns
Input Clock (K/K and C/C) HIGH
1.6
–
2.0
–
2.4
–
ns
Input Clock (K/K and C/C) LOW
1.6
–
2.0
–
2.4
–
ns
K Clock Rise to K Clock Rise and C to C Rise
(rising edge to rising edge)
1.8
–
2.2
–
2.7
–
ns
t
KHCH
t
KHCH
K/K Clock Rise to C/C Clock Rise (rising edge
to rising edge)
0.0
1.8
0.0
2.2
0.0
2.7
ns
Setup Times
t
SA
t
SC
t
SCDDR
t
AVKH
t
IVKH
t
IVKH
Address Setup to K Clock Rise
0.35
–
0.4
–
0.5
–
ns
Control Setup to K Clock Rise (RPS, WPS)
0.35
–
0.4
–
0.5
–
ns
Double Data Rate Control Setup to Clock
(K, K) Rise (BWS
0
, BWS
1
, BWS
3
, BWS
4
)
D
[X:0]
Setup to Clock (K/K) Rise
0.35
–
0.4
–
0.5
–
ns
t
SD
Hold Times
t
DVKH
0.35
–
0.4
–
0.5
–
ns
t
HA
t
HC
t
HCDDR
t
KHAX
t
KHIX
t
KHIX
Address Hold after K Clock Rise
0.35
–
0.4
–
0.5
–
ns
Control Hold after K Clock Rise (RPS, WPS)
0.35
–
0.4
–
0.5
–
ns
Double Data Rate Control Hold after Clock
(K, K) Rise (BWS
0
, BWS
1
, BWS
3
, BWS
4
)
D
[X:0]
Hold after Clock (K/K) Rise
0.35
–
0.4
–
0.5
–
ns
t
HD
Output Times
t
KHDX
0.35
–
0.4
–
0.5
–
ns
t
CO
t
CHQV
C/C Clock Rise (or K/K in Single Clock Mode)
to Data Valid
–
0.45
–
0.45
–
0.50
ns
t
DOH
t
CHQX
Data Output Hold after Output C/C Clock Rise
(Active to Active)
–0.45
–
–0.45
–
-0.50
–
ns
t
CCQO
t
CQOH
t
CQD
t
CQDOH
t
CHZ
t
CHCQV
t
CHCQX
t
CQHQV
t
CQHQX
t
CHQZ
C/C Clock Rise to Echo Clock Valid
–
0.45
–
0.45
–
0.50
ns
Echo Clock Hold after C/C Clock Rise
–0.45
–
–0.45
–
–0.50
–
ns
Echo Clock High to Data Valid
–
0.30
–
0.35
–
0.40
ns
Echo Clock High to Data Invalid
–0.30
–
–0.35
–
–0.40
–
ns
Clock (C/C) Rise to High-Z
(Active to High-Z)
[24,25]
Clock (C/C) Rise to Low-Z
[24,25]
–
0.45
–
0.45
–
0.50
ns
t
CLZ
DLL Timing
t
CHQX1
–0.45
–
–0.45
–
–0.50
–
ns
t
KC Var
t
KC lock
t
KC Reset
t
KC Var
t
KC lock
t
KC Reset
Clock Phase Jitter
–
0.20
–
0.20
–
0.20
ns
DLL Lock Time (K, C)
1024
–
1024
–
1024
–
cycles
K Static to DLL Reset
30
–
30
–
30
–
ns
Notes:
23.All devices can operate at clock frequencies as low as 119 MHz. When a part with a maximum frequency above 133 MHz is operating at a lower clock frequency,
it requires the input timings of the frequency range in which it is being operated and outputs data with the output timings of that frequency range.
24.t
, t
, are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured
±
100 mV from steady-state voltage.
25.At any voltage and temperature t
is less than t
CLZ
and t
CHZ
less than t
CO
.
26.This part has a voltage regulator internally; t
POWER
DD
minimum initially before a read or write operation
can be initiated.
27.For D2 data signal on CY7C1425AV18 device, t
SD
is 0.5 ns for 200 MHz, and 250 MHz frequencies.
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