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參數(shù)資料
| 型號： | CY7C1410AV18_07 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 36-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture |
| 中文描述： | 的36 - Mbit QDR - II型⑩SRAM的2字突發(fā)結(jié)構(gòu) |
| 文件頁數(shù)： | 10/25頁 |
| 文件大小： | 1021K |
| 代理商： | CY7C1410AV18_07 |
CY7C1410AV18
CY7C1425AV18
CY7C1412AV18
CY7C1414AV18
Document #: 38-05615 Rev. *D
Page 10 of 25
L
H
–
L-H
During the data portion of a write sequence
:
CY7C1410AV18
only the lower nibble (D
[3:0]
) is written into the device. D
[7:4]
remains unaltered,
CY7C1412AV18
only the lower byte (D
[8:0]
) is written into the device. D
[17:9]
remains unaltered.
During the data portion of a write sequence
:
CY7C1410AV18
only the upper nibble (D
[7:4]
) is written into the device. D
[3:0]
remains unaltered,
CY7C1412AV18
only the upper byte (D
[17:9]
) is written into the device. D
[8:0]
remains unaltered.
During the data portion of a write sequence
:
CY7C1410AV18
only the upper nibble (D
[7:4]
) is written into the device. D
[3:0]
remains unaltered,
CY7C1412AV18
only the upper byte (D
[17:9]
) is written into the device. D
[8:0]
remains unaltered.
No data is written into the devices during this portion of a write operation.
No data is written into the devices during this portion of a write operation.
H
L
L-H
–
H
L
–
L-H
H
H
H
H
L-H
–
–
L-H
Write Cycle Descriptions
(CY7C1414AV18)
[2, 8]
BWS
0
BWS
1
BWS
2
BWS
3
K
K
Comments
L
L
L
L
L-H
–
During the data portion of a write sequence, all four bytes (D
[35:0]
) are
written into the device.
During the data portion of a write sequence, all four bytes (D
[35:0]
) are
written into the device.
During the data portion of a write sequence, only the lower byte (D
[8:0]
)
is written into the device. D
[35:9]
remains unaltered.
During the data portion of a write sequence, only the lower byte (D
[8:0]
)
is written into the device. D
[35:9]
remains unaltered.
During the data portion of a write sequence, only the byte (D
[17:9]
) is
written into the device. D
[8:0]
and D
[35:18]
remains unaltered.
During the data portion of a write sequence, only the byte (D
[17:9]
) is
written into the device. D
[8:0]
and D
[35:18]
remains unaltered.
During the data portion of a write sequence, only the byte (D
[26:18]
) is
written into the device. D
[17:0]
and D
[35:27]
remains unaltered.
During the data portion of a write sequence, only the byte (D
[26:18]
) is
written into the device. D
[17:0]
and D
[35:27]
remains unaltered.
During the data portion of a write sequence, only the byte (D
[35:27]
) is
written into the device. D
[26:0]
remains unaltered.
During the data portion of a write sequence, only the byte (D
[35:27]
) is
written into the device. D
[26:0]
remains unaltered.
No data is written into the device during this portion of a write operation.
No data is written into the device during this portion of a write operation.
L
L
L
L
–
L-H
L
H
H
H
L-H
–
L
H
H
H
–
L-H
H
L
H
H
L-H
–
H
L
H
H
–
L-H
H
H
L
H
L-H
–
H
H
L
H
–
L-H
H
H
H
L
L-H
H
H
H
L
–
L-H
H
H
H
H
H
H
H
H
L-H
–
–
L-H
Write Cycle Descriptions
(CY7C1425AV18)
BWS
0
K
K
Comments
L
L-H
–
During the data portion of a write sequence
:
CY7C1425AV18 - the single byte (D[8:0]) is written into the device
During the data portion of a write sequence
:
CY7C1425AV18 - the single byte (D[8:0]) is written into the device
No data is written into the devices during this portion of a Write operation.
No data is written into the devices during this portion of a Write operation.
L
–
L-H
H
H
L-H
–
–
L-H
Write Cycle Descriptions
(CY7C1410AV18 and CY7C1412AV18) (continued)
[2, 8]
BWS
0
/
NWS
0
BWS
1
/
NWS
1
K
K
Comments
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1410AV18-167BZI | 36-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture |
| CY7C1410AV18-167BZXC | 36-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture |
| CY7C1410AV18-167BZXI | 36-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture |
| CY7C1410AV18-200BZI | 36-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture |
| CY7C1410AV18-200BZXC | 36-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture |
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