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參數(shù)資料
| 型號： | CY7C1410AV18_07 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 36-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture |
| 中文描述： | 的36 - Mbit QDR - II型⑩SRAM的2字突發(fā)結(jié)構(gòu) |
| 文件頁數(shù)： | 16/25頁 |
| 文件大?。?/td> | 1021K |
| 代理商： | CY7C1410AV18_07 |
CY7C1410AV18
CY7C1425AV18
CY7C1412AV18
CY7C1414AV18
Document #: 38-05615 Rev. *D
Page 16 of 25
Identification Register Definitions
Instruction Field
Revision Number
(31:29)
Cypress Device ID
(28:12)
Cypress JEDEC ID
(11:1)
Value
Description
Version number.
CY7C1410AV18
000
CY7C1425AV18
000
CY7C1412AV18
000
CY7C1414AV18
000
11010011010000111 11010011010001111 11010011010010111 11010011010100111 Defines the type of
SRAM.
Unique identifi-
cation of SRAM
vendor.
Indicates the
presence of an ID
register.
00000110100
00000110100
00000110100
00000110100
ID Register Presence
(0)
1
1
1
1
Scan Register Sizes
Register Name
Instruction
Bypass
ID
Boundary Scan Cells
Bit Size
3
1
32
109
Instruction Codes
Instruction
Code
Description
EXTEST
IDCODE
000
001
Captures the Input/Output ring contents.
Loads the ID register with the vendor ID code and places the register between
TDI and TDO. This operation does not affect SRAM operation.
Captures the Input/Output contents. Places the boundary scan register
between TDI and TDO. Forces all SRAM output drivers to a High-Z state.
Do Not Use: This instruction is reserved for future use.
Captures the Input/Output ring contents. Places the boundary scan register
between TDI and TDO. Does not affect the SRAM operation.
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not
affect SRAM operation.
SAMPLE Z
010
RESERVED
SAMPLE/PRELOAD
011
100
RESERVED
RESERVED
BYPASS
101
110
111
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1410AV18-167BZI | 36-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture |
| CY7C1410AV18-167BZXC | 36-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture |
| CY7C1410AV18-167BZXI | 36-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture |
| CY7C1410AV18-200BZI | 36-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture |
| CY7C1410AV18-200BZXC | 36-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture |
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| CY7C1411BV18-250BZC | 功能描述:靜態(tài)隨機(jī)存取存儲器 1Mx36 QDR II Burst 4 靜態(tài)隨機(jī)存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1411KV18-250BZC | 功能描述:靜態(tài)隨機(jī)存取存儲器 36Mb QDR II 靜態(tài)隨機(jī)存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1411KV18-300BZC | 功能描述:靜態(tài)隨機(jī)存取存儲器 36MB (4Mx8) 1.8v 300MHz QDR II 靜態(tài)隨機(jī)存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1411SC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1411SV18-250BZC | 功能描述:靜態(tài)隨機(jī)存取存儲器 NV靜態(tài)隨機(jī)存取存儲器 250 MHz 1.8V RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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