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| 型號： | CY7C1380C-167AI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 18-Mb (512K x 36/1M x 18) Pipelined SRAM |
| 中文描述： | 512K X 36 CACHE SRAM, 3.4 ns, PQFP100 |
| 封裝： | 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100 |
| 文件頁數(shù)： | 9/36頁 |
| 文件大?。?/td> | 788K |
| 代理商： | CY7C1380C-167AI |
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CY7C1380C
CY7C1382C
Document #: 38-05237 Rev. *D
Page 9 of 36
CY7C1382C:Pin Definitions
Name
TQFP
BGA
fBGA
I/O
Description
A
0
, A
1
, A
37,36,32,
33,34,35,
42,43,44,
45,46,47,
48,49,50,
80,81,82,
99,100
P4,N4,
A2,B2,
C2,R2,
T2,A3,
B3,C3,
T3,A5,
B5,C5,
T5,A6,
B6,C6,
R6,T6
R6,P6,A2,
A10,A11,
B2,B10,P3,P4,
N6,P8,P9,
P10,P11,
R3,R4,R8,R9,
R10,
R11
Input-
Synchronous
Address Inputs used to select one of the 512K
address locations
. Sampled at the rising edge of
the CLK if ADSP or ADSC is active LOW, and CE
1
,
CE
2
, and
CE
3
are sampled active. A1: A0 are fed
to the two-bit counter..
BW
A,
BW
B
93,94
G3,L5
B5,A4
Input-
Synchronous
Byte Write Select Inputs, active LOW
. Qualified
with BWE to conduct byte writes to the SRAM.
Sampled on the rising edge of CLK.
Global Write Enable Input, active LOW
. When
asserted LOW on the rising edge of CLK, a global
write is conducted (ALL bytes are written,
regardless of the values on BW
X
and BWE).
GW
88
H4
B7
Input-
Synchronous
BWE
87
M4
A7
Input-
Synchronous
Byte Write Enable Input, active LOW
. Sampled
on the rising edge of CLK. This signal must be
asserted LOW to conduct a byte write.
CLK
89
K4
B6
Input-
Clock
Clock Input
. Used to capture all synchronous
inputs to the device. Also used to increment the
burst counter when ADV is asserted LOW, during a
burst operation.
CE
1
98
E4
A3
Input-
Synchronous
Chip Enable 1 Input, active LOW
. Sampled on the
rising edge of CLK. Used in conjunction with CE
2
and CE
3
to select/deselect the device. ADSP is
ignored if CE
1
is HIGH.
CE
2[2]
97
-
B3
Input-
Synchronous
Chip Enable 2 Input, active HIGH
. Sampled on
the rising edge of CLK. Used in conjunction with
CE
1
and CE
3
to select/deselect the device.
CE
3 [2]
92
-
A6
Input-
Synchronous
Chip Enable 3 Input, active LOW
. Sampled on the
rising edge of CLK. Used in conjunction with CE
1
and
CE
2
to select/deselect the device. Not available
for AJ package version.Not connected for BGA.
Where referenced, CE
3
is assumed active
throughout this document for BGA.
OE
86
F4
B8
Input-
Asynchronous
Output Enable, asynchronous input, active
LOW
. Controls the direction of the I/O pins. When
LOW, the I/O pins behave as outputs. When
deasserted HIGH, I/O pins are tri-stated, and act as
input data pins. OE is masked during the first clock
of a read cycle when emerging from a deselected
state.
ADV
83
G4
A9
Input-
Synchronous
Advance Input signal, sampled on the rising
edge of CLK, active LOW
. When asserted, it
automatically increments the address in a burst
cycle.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1380C-167BGC | 18-Mb (512K x 36/1M x 18) Pipelined SRAM |
| CY7C1380C-167BGI | 18-Mb (512K x 36/1M x 18) Pipelined SRAM |
| CY7C1380C-200AC | 18-Mb (512K x 36/1M x 18) Pipelined SRAM |
| CY7C1380C-200BGC | 18-Mb (512K x 36/1M x 18) Pipelined SRAM |
| CY7C1380C-250AC | 18-Mb (512K x 36/1M x 18) Pipelined SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1380C-167BGC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1380C-167BGCT | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1380C-167BZC | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC SGL 3.3V 18MBIT 512KX36 3.4NS 165FBGA - Bulk |
| CY7C1380C-167BZI | 功能描述:IC SRAM 512KX36 SYNC 165-FBGA RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:4K (512 x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:2.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:8-MFP 包裝:帶卷 (TR) |
| CY7C1380C-200AC | 制造商:Rochester Electronics LLC 功能描述:16MB (512KX36) 3.3V SYNC-PIPE (SINGLE CYCLE DESELECT) SRAM - Bulk |
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